arch.h File Reference

IA-32 specific kernel interface header This header contains the IA-32 specific kernel interface. It is included by the generic kernel interface header (include/arch/cpu.h) More...

#include "sys_io.h"
#include <stdbool.h>
#include <kernel_structs.h>
#include <arch/common/ffs.h>
#include <sys/util.h>
#include <arch/x86/ia32/gdbstub.h>
#include <arch/x86/ia32/thread.h>
#include <arch/x86/ia32/syscall.h>
#include <stddef.h>
#include <arch/common/addr_types.h>
#include <arch/x86/ia32/segmentation.h>
#include <pm/pm.h>

Go to the source code of this file.

Data Structures
struct	s_isrList
struct	nanoEsf
	Exception Stack Frame. More...

Macros
#define	CODE_SEG   0x08
#define	DATA_SEG   0x10
#define	MAIN_TSS   0x18
#define	DF_TSS   0x20
#define	GS_TLS_SEG   (0x38 | 0x03)
#define	MK_ISR_NAME(x)   __isr__##x
#define	NANO_CPU_INT_REGISTER(r, n, p, v, d)
	Connect a routine to an interrupt vector. More...
#define	IRQSTUBS_TEXT_SECTION   ".text.irqstubs"
#define	ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p)
#define	ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p)
#define	ARCH_ISR_DIRECT_PM()   do { } while (false)
#define	ARCH_ISR_DIRECT_HEADER()   arch_isr_direct_header()
#define	ARCH_ISR_DIRECT_FOOTER(swap)   arch_isr_direct_footer(swap)
#define	ARCH_ISR_DIRECT_DECLARE(name)
#define	NANO_SOFT_IRQ   ((unsigned int) (-1))
#define	ARCH_EXCEPT(reason_p)
#define	ARCH_DYMANIC_OBJ_K_THREAD_ALIGNMENT   (sizeof(void *))

Typedefs
typedef struct s_isrList	ISR_LIST

Functions
static void	arch_isr_direct_header (void)
void	arch_isr_direct_footer_swap (unsigned int key)
static void	arch_isr_direct_footer (int swap)
static ALWAYS_INLINE unsigned int	arch_irq_lock (void)

Detailed Description

IA-32 specific kernel interface header This header contains the IA-32 specific kernel interface. It is included by the generic kernel interface header (include/arch/cpu.h)

Macro Definition Documentation

ARCH_DYMANIC_OBJ_K_THREAD_ALIGNMENT

#define ARCH_DYMANIC_OBJ_K_THREAD_ALIGNMENT   (sizeof(void *))

ARCH_EXCEPT

#define ARCH_EXCEPT

(

reason_p

)

Value:

        do { \
        __asm__ volatile( \
                "push %[reason]\n\t" \
                "int %[vector]\n\t" \
                : \
                : [vector] "i" (Z_X86_OOPS_VECTOR), \
                  [reason] "i" (reason_p)); \
        CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ \
} while (false)

ARCH_IRQ_CONNECT

#define ARCH_IRQ_CONNECT	(		irq_p,
			priority_p,
			isr_p,
			isr_param_p,
			flags_p
	)

Value:

{ \
        __asm__ __volatile__(                                                   \
                ".pushsection .intList\n\t" \
                ".long %c[isr]_irq%c[irq]_stub\n\t"     /* ISR_LIST.fnc */ \
                ".long %c[irq]\n\t"             /* ISR_LIST.irq */ \
                ".long %c[priority]\n\t"        /* ISR_LIST.priority */ \
                ".long %c[vector]\n\t"          /* ISR_LIST.vec */ \
                ".long 0\n\t"                   /* ISR_LIST.dpl */ \
                ".long 0\n\t"                   /* ISR_LIST.tss */ \
                ".popsection\n\t" \
                ".pushsection " IRQSTUBS_TEXT_SECTION "\n\t" \
                ".global %c[isr]_irq%c[irq]_stub\n\t" \
                "%c[isr]_irq%c[irq]_stub:\n\t" \
                "pushl %[isr_param]\n\t" \
                "pushl %[isr]\n\t" \
                "jmp _interrupt_enter\n\t" \
                ".popsection\n\t" \
                : \
                : [isr] "i" (isr_p), \
                  [isr_param] "i" (isr_param_p), \
                  [priority] "i" (priority_p), \
                  [vector] "i" _VECTOR_ARG(irq_p), \
                  [irq] "i" (irq_p)); \
        z_irq_controller_irq_config(Z_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), \
                                   (flags_p)); \
}

ARCH_IRQ_DIRECT_CONNECT

#define ARCH_IRQ_DIRECT_CONNECT	(		irq_p,
			priority_p,
			isr_p,
			flags_p
	)

Value:

{ \
        NANO_CPU_INT_REGISTER(isr_p, irq_p, priority_p, -1, 0); \
        z_irq_controller_irq_config(Z_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), \
                                   (flags_p)); \
}

ARCH_ISR_DIRECT_DECLARE

#define ARCH_ISR_DIRECT_DECLARE

(

name

)

Value:

        static inline int name##_body(void); \
        __attribute__ ((interrupt)) void name(void *stack_frame) \
        { \
                ARG_UNUSED(stack_frame); \
                int check_reschedule; \
                ISR_DIRECT_HEADER(); \
                check_reschedule = name##_body(); \
                ISR_DIRECT_FOOTER(check_reschedule); \
        } \
        static inline int name##_body(void)

ARCH_ISR_DIRECT_FOOTER

#define ARCH_ISR_DIRECT_FOOTER

(

swap

)

arch_isr_direct_footer(swap)

ARCH_ISR_DIRECT_HEADER

#define ARCH_ISR_DIRECT_HEADER

(

)

arch_isr_direct_header()

ARCH_ISR_DIRECT_PM

#define ARCH_ISR_DIRECT_PM

(

)

do { } while (false)

CODE_SEG

#define CODE_SEG   0x08

DATA_SEG

#define DATA_SEG   0x10

DF_TSS

#define DF_TSS   0x20

GS_TLS_SEG

#define GS_TLS_SEG   (0x38 | 0x03)

IRQSTUBS_TEXT_SECTION

#define IRQSTUBS_TEXT_SECTION   ".text.irqstubs"

MAIN_TSS

#define MAIN_TSS   0x18

MK_ISR_NAME

#define MK_ISR_NAME

(

x

)

__isr__##x

Macro used internally by NANO_CPU_INT_REGISTER and NANO_CPU_INT_REGISTER_ASM. Not meant to be used explicitly by platform, driver or application code.

NANO_CPU_INT_REGISTER

#define NANO_CPU_INT_REGISTER	(		r,
			n,
			p,
			v,
			d
	)

Value:

         static ISR_LIST __attribute__((section(".intList"))) \
                         __attribute__((used)) MK_ISR_NAME(r) = \
                        { \
                                .fnc = &(r), \
                                .irq = (n), \
                                .priority = (p), \
                                .vec = (v), \
                                .dpl = (d), \
                                .tss = 0 \
                        }

Connect a routine to an interrupt vector.

This macro "connects" the specified routine, r, to the specified interrupt vector, v using the descriptor privilege level d. On the IA-32 architecture, an interrupt vector is a value from 0 to 255. This macro populates the special intList section with the address of the routine, the vector number and the descriptor privilege level. The genIdt tool then picks up this information and generates an actual IDT entry with this information properly encoded.

The d argument specifies the privilege level for the interrupt-gate descriptor; (hardware) interrupts and exceptions should specify a level of 0, whereas handlers for user-mode software generated interrupts should specify 3.

Parameters

r	Routine to be connected
n	IRQ number
p	IRQ priority
v	Interrupt Vector
d	Descriptor Privilege Level

Returns

N/A

NANO_SOFT_IRQ

#define NANO_SOFT_IRQ   ((unsigned int) (-1))

The NANO_SOFT_IRQ macro must be used as the value for the irq parameter to NANO_CPU_INT_REGISTER when connecting to an interrupt that does not correspond to any IRQ line (such as spurious vector or SW IRQ)

Typedef Documentation

ISR_LIST

typedef struct s_isrList ISR_LIST

Function Documentation

arch_irq_lock()

static ALWAYS_INLINE unsigned int arch_irq_lock ( void  )

static

arch_isr_direct_footer()

static void arch_isr_direct_footer ( int  swap )

inlinestatic

arch_isr_direct_footer_swap()

void arch_isr_direct_footer_swap

(

unsigned int

key

)

arch_isr_direct_header()

static void arch_isr_direct_header ( void  )

inlinestatic