Zephyr API Documentation  2.7.0-rc2
A Scalable Open Source RTOS
cache.h File Reference
#include <kernel.h>
#include <kernel_structs.h>
#include <syscalls/cache.h>

Go to the source code of this file.

Macros

#define K_CACHE_WB   BIT(0)
 
#define K_CACHE_INVD   BIT(1)
 
#define K_CACHE_WB_INVD   (K_CACHE_WB | K_CACHE_INVD)
 
#define cache_data_enable   arch_dcache_enable
 
#define cache_data_disable   arch_dcache_disable
 
#define cache_instr_enable   arch_icache_enable
 
#define cache_instr_disable   arch_icache_disable
 
#define cache_data_all(op)   arch_dcache_all(op)
 
#define cache_data_range(addr, size, op)   arch_dcache_range(addr, size, op)
 
#define cache_instr_all(op)   arch_icache_all(op)
 
#define cache_instr_range(addr, size, op)   arch_icache_range(addr, size, op)
 
#define cache_data_line_size_get   arch_dcache_line_size_get
 
#define cache_instr_line_size_get   arch_icache_line_size_get
 
#define CPU   DT_PATH(cpus, cpu_0)
 

Functions

int sys_cache_data_all (int op)
 
int sys_cache_data_range (void *addr, size_t size, int op)
 
int sys_cache_instr_all (int op)
 
int sys_cache_instr_range (void *addr, size_t size, int op)
 
static size_t sys_cache_data_line_size_get (void)
 Get the d-cache line size. More...
 
static size_t sys_cache_instr_line_size_get (void)
 

Macro Definition Documentation

◆ cache_data_all

#define cache_data_all (   op)    arch_dcache_all(op)

◆ cache_data_disable

#define cache_data_disable (   void)    arch_dcache_disable

◆ cache_data_enable

#define cache_data_enable (   void)    arch_dcache_enable

◆ cache_data_line_size_get

#define cache_data_line_size_get   arch_dcache_line_size_get

◆ cache_data_range

#define cache_data_range (   addr,
  size,
  op 
)    arch_dcache_range(addr, size, op)

◆ cache_instr_all

#define cache_instr_all (   op)    arch_icache_all(op)

◆ cache_instr_disable

#define cache_instr_disable (   void)    arch_icache_disable

◆ cache_instr_enable

#define cache_instr_enable (   void)    arch_icache_enable

◆ cache_instr_line_size_get

#define cache_instr_line_size_get   arch_icache_line_size_get

◆ cache_instr_range

#define cache_instr_range (   addr,
  size,
  op 
)    arch_icache_range(addr, size, op)

◆ CPU

#define CPU   DT_PATH(cpus, cpu_0)

◆ K_CACHE_INVD

#define K_CACHE_INVD   BIT(1)

◆ K_CACHE_WB

#define K_CACHE_WB   BIT(0)

Common operations for the caches

WB means write-back and intends to transfer dirty cache lines to memory in a copy-back cache policy. May be a no-op in write-back cache policy.

INVD means invalidate and will mark cache lines as not valid. A future access to the associated address is guaranteed to generate a memory fetch.

◆ K_CACHE_WB_INVD

#define K_CACHE_WB_INVD   (K_CACHE_WB | K_CACHE_INVD)

Function Documentation

◆ sys_cache_data_all()

int sys_cache_data_all ( int  op)

◆ sys_cache_data_line_size_get()

static size_t sys_cache_data_line_size_get ( void  )
inlinestatic

Get the d-cache line size.

The API is provided to get the d-cache line size.

Returns
size of the d-cache line or 0 if the d-cache is not enabled.

◆ sys_cache_data_range()

int sys_cache_data_range ( void addr,
size_t  size,
int  op 
)

◆ sys_cache_instr_all()

int sys_cache_instr_all ( int  op)

◆ sys_cache_instr_line_size_get()

static size_t sys_cache_instr_line_size_get ( void  )
inlinestatic

◆ sys_cache_instr_range()

int sys_cache_instr_range ( void addr,
size_t  size,
int  op 
)