Zephyr API Documentation  2.7.0-rc2
A Scalable Open Source RTOS
cache.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2015 Wind River Systems, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_CACHE_H_
8#define ZEPHYR_INCLUDE_CACHE_H_
9
10#include <kernel.h>
11#include <kernel_structs.h>
12
13#ifdef __cplusplus
14extern "C" {
15#endif
16
27#define K_CACHE_WB BIT(0)
28#define K_CACHE_INVD BIT(1)
29#define K_CACHE_WB_INVD (K_CACHE_WB | K_CACHE_INVD)
30
31#if defined(CONFIG_HAS_EXTERNAL_CACHE)
32
33/* Driver interface mirrored in include/drivers/cache.h */
34
35/* Enable d-cache */
36extern void cache_data_enable(void);
37
38/* Disable d-cache */
39extern void cache_data_disable(void);
40
41/* Enable i-cache */
42extern void cache_instr_enable(void);
43
44/* Disable i-cache */
45extern void cache_instr_disable(void);
46
47/* Write-back / Invalidate / Write-back + Invalidate all d-cache */
48extern int cache_data_all(int op);
49
50/* Write-back / Invalidate / Write-back + Invalidate d-cache lines */
51extern int cache_data_range(void *addr, size_t size, int op);
52
53/* Write-back / Invalidate / Write-back + Invalidate all i-cache */
54extern int cache_instr_all(int op);
55
56/* Write-back / Invalidate / Write-back + Invalidate i-cache lines */
57extern int cache_instr_range(void *addr, size_t size, int op);
58
59#else
60
61/* Hooks into arch code */
62
63#define cache_data_enable arch_dcache_enable
64#define cache_data_disable arch_dcache_disable
65#define cache_instr_enable arch_icache_enable
66#define cache_instr_disable arch_icache_disable
67#define cache_data_all(op) arch_dcache_all(op)
68#define cache_data_range(addr, size, op) arch_dcache_range(addr, size, op)
69#define cache_instr_all(op) arch_icache_all(op)
70#define cache_instr_range(addr, size, op) arch_icache_range(addr, size, op)
71#define cache_data_line_size_get arch_dcache_line_size_get
72#define cache_instr_line_size_get arch_icache_line_size_get
73
74#endif
75
76__syscall int sys_cache_data_all(int op);
77static inline int z_impl_sys_cache_data_all(int op)
78{
79#if defined(CONFIG_CACHE_MANAGEMENT)
80 return cache_data_all(op);
81#endif
82 ARG_UNUSED(op);
83
84 return -ENOTSUP;
85}
86
87__syscall int sys_cache_data_range(void *addr, size_t size, int op);
88static inline int z_impl_sys_cache_data_range(void *addr, size_t size, int op)
89{
90#if defined(CONFIG_CACHE_MANAGEMENT)
91 return cache_data_range(addr, size, op);
92#endif
93 ARG_UNUSED(addr);
94 ARG_UNUSED(size);
95 ARG_UNUSED(op);
96
97 return -ENOTSUP;
98}
99
100__syscall int sys_cache_instr_all(int op);
101static inline int z_impl_sys_cache_instr_all(int op)
102{
103#if defined(CONFIG_CACHE_MANAGEMENT)
104 return cache_instr_all(op);
105#endif
106 ARG_UNUSED(op);
107
108 return -ENOTSUP;
109}
110
111__syscall int sys_cache_instr_range(void *addr, size_t size, int op);
112static inline int z_impl_sys_cache_instr_range(void *addr, size_t size, int op)
113{
114#if defined(CONFIG_CACHE_MANAGEMENT)
115 return cache_instr_range(addr, size, op);
116#endif
117 ARG_UNUSED(addr);
118 ARG_UNUSED(size);
119 ARG_UNUSED(op);
120
121 return -ENOTSUP;
122}
123
124#ifdef CONFIG_LIBMETAL
125static inline void sys_cache_flush(void *addr, size_t size)
126{
127 sys_cache_data_range(addr, size, K_CACHE_WB);
128}
129#endif
130
131#define CPU DT_PATH(cpus, cpu_0)
132
141static inline size_t sys_cache_data_line_size_get(void)
142{
143#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
145#elif (CONFIG_DCACHE_LINE_SIZE != 0)
146 return CONFIG_DCACHE_LINE_SIZE;
147#else
148 return DT_PROP_OR(CPU, d_cache_line_size, 0);
149#endif
150}
151
152/*
153 *
154 * @brief Get the i-cache line size.
155 *
156 * The API is provided to get the i-cache line size.
157 *
158 * @return size of the i-cache line or 0 if the i-cache is not enabled.
159 */
160static inline size_t sys_cache_instr_line_size_get(void)
161{
162#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
164#elif (CONFIG_ICACHE_LINE_SIZE != 0)
165 return CONFIG_ICACHE_LINE_SIZE;
166#else
167 return DT_PROP_OR(CPU, i_cache_line_size, 0);
168#endif
169}
170
171#include <syscalls/cache.h>
172#ifdef __cplusplus
173}
174#endif
175
176#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
#define cache_data_all(op)
Definition: cache.h:67
#define cache_data_range(addr, size, op)
Definition: cache.h:68
#define cache_instr_range(addr, size, op)
Definition: cache.h:70
#define cache_instr_disable
Definition: cache.h:66
#define cache_instr_enable
Definition: cache.h:65
#define K_CACHE_WB
Definition: cache.h:27
int sys_cache_data_all(int op)
#define cache_instr_all(op)
Definition: cache.h:69
int sys_cache_instr_range(void *addr, size_t size, int op)
int sys_cache_instr_all(int op)
static size_t sys_cache_data_line_size_get(void)
Get the d-cache line size.
Definition: cache.h:141
int sys_cache_data_range(void *addr, size_t size, int op)
#define CPU
Definition: cache.h:131
#define cache_data_enable
Definition: cache.h:63
static size_t sys_cache_instr_line_size_get(void)
Definition: cache.h:160
#define cache_instr_line_size_get
Definition: cache.h:72
#define cache_data_disable
Definition: cache.h:64
#define cache_data_line_size_get
Definition: cache.h:71
#define DT_PROP_OR(node_id, prop, default_value)
Like DT_PROP(), but with a fallback to default_value.
Definition: devicetree.h:640
#define ENOTSUP
Definition: errno.h:115