Zephyr API Documentation  2.7.0-rc2
A Scalable Open Source RTOS
arm_mpu_v8m.h File Reference

Go to the source code of this file.

Data Structures

struct  arm_mpu_region_attr
 
struct  k_mem_partition_attr_t
 

Macros

#define P_RW_U_NA   0x0
 
#define P_RW_U_NA_Msk   ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
 
#define P_RW_U_RW   0x1
 
#define P_RW_U_RW_Msk   ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
 
#define FULL_ACCESS   0x1
 
#define FULL_ACCESS_Msk   ((FULL_ACCESS << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
 
#define P_RO_U_NA   0x2
 
#define P_RO_U_NA_Msk   ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
 
#define P_RO_U_RO   0x3
 
#define P_RO_U_RO_Msk   ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
 
#define RO   0x3
 
#define RO_Msk   ((RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
 
#define NOT_EXEC   MPU_RBAR_XN_Msk
 
#define NON_SHAREABLE   0x0
 
#define NON_SHAREABLE_Msk    ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
 
#define OUTER_SHAREABLE   0x2
 
#define OUTER_SHAREABLE_Msk    ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
 
#define INNER_SHAREABLE   0x3
 
#define INNER_SHAREABLE_Msk    ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
 
#define REGION_LIMIT_ADDR(base, size)    (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk)
 
#define R_NON_W_NON   0x0 /* Do not allocate Read/Write */
 
#define R_NON_W_ALLOC   0x1 /* Do not allocate Read, Allocate Write */
 
#define R_ALLOC_W_NON   0x2 /* Allocate Read, Do not allocate Write */
 
#define R_ALLOC_W_ALLOC   0x3 /* Allocate Read/Write */
 
#define NORMAL_O_WT_NT   0x80 /* Normal, Outer Write-through non-transient */
 
#define NORMAL_O_WB_NT   0xC0 /* Normal, Outer Write-back non-transient */
 
#define NORMAL_O_NON_C   0x40 /* Normal, Outer Non-Cacheable */
 
#define NORMAL_I_WT_NT   0x08 /* Normal, Inner Write-through non-transient */
 
#define NORMAL_I_WB_NT   0x0C /* Normal, Inner Write-back non-transient */
 
#define NORMAL_I_NON_C   0x04 /* Normal, Inner Non-Cacheable */
 
#define NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS
 
#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS
 
#define NORMAL_OUTER_INNER_NON_CACHEABLE
 
#define MPU_CACHE_ATTRIBUTES_FLASH    NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS
 
#define MPU_CACHE_ATTRIBUTES_SRAM    NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS
 
#define MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE    NORMAL_OUTER_INNER_NON_CACHEABLE
 
#define MPU_MAIR_ATTR_FLASH   MPU_CACHE_ATTRIBUTES_FLASH
 
#define MPU_MAIR_INDEX_FLASH   0
 
#define MPU_MAIR_ATTR_SRAM   MPU_CACHE_ATTRIBUTES_SRAM
 
#define MPU_MAIR_INDEX_SRAM   1
 
#define MPU_MAIR_ATTR_SRAM_NOCACHE   MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE
 
#define MPU_MAIR_INDEX_SRAM_NOCACHE   2
 
#define REGION_RAM_ATTR(base, size)
 
#define REGION_FLASH_ATTR(base, size)
 
#define K_MEM_PARTITION_P_RW_U_RW
 
#define K_MEM_PARTITION_P_RW_U_NA
 
#define K_MEM_PARTITION_P_RO_U_RO
 
#define K_MEM_PARTITION_P_RO_U_NA
 
#define K_MEM_PARTITION_P_RWX_U_RWX
 
#define K_MEM_PARTITION_P_RX_U_RX
 
#define K_MEM_PARTITION_IS_WRITABLE(attr)
 
#define K_MEM_PARTITION_IS_EXECUTABLE(attr)    (!((attr.rbar) & (NOT_EXEC)))
 
#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE
 
#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE
 
#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE
 
#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE
 
#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE
 
#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE
 

Typedefs

typedef struct arm_mpu_region_attr arm_mpu_region_attr_t
 

Macro Definition Documentation

◆ FULL_ACCESS

#define FULL_ACCESS   0x1

◆ FULL_ACCESS_Msk

#define FULL_ACCESS_Msk   ((FULL_ACCESS << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

◆ INNER_SHAREABLE

#define INNER_SHAREABLE   0x3

◆ INNER_SHAREABLE_Msk

#define INNER_SHAREABLE_Msk    ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)

◆ K_MEM_PARTITION_IS_EXECUTABLE

#define K_MEM_PARTITION_IS_EXECUTABLE (   attr)     (!((attr.rbar) & (NOT_EXEC)))

◆ K_MEM_PARTITION_IS_WRITABLE

#define K_MEM_PARTITION_IS_WRITABLE (   attr)
Value:
({ \
int __is_writable__; \
switch (attr.rbar & MPU_RBAR_AP_Msk) { \
case P_RW_U_RW_Msk: \
case P_RW_U_NA_Msk: \
__is_writable__ = 1; \
break; \
default: \
__is_writable__ = 0; \
} \
__is_writable__; \
})
#define MPU_RBAR_AP_Msk
Definition: arm_mpu.h:24
#define P_RW_U_NA_Msk
Definition: arm_mpu_v8m.h:25
#define P_RW_U_RW_Msk
Definition: arm_mpu_v8m.h:31

◆ K_MEM_PARTITION_P_RO_U_NA

#define K_MEM_PARTITION_P_RO_U_NA
Value:
uint32_t k_mem_partition_attr_t
Definition: arch.h:267
#define MPU_MAIR_INDEX_SRAM
Definition: arm_mpu_v8m.h:108
#define NOT_EXEC
Definition: arm_mpu_v8m.h:46
#define P_RO_U_NA_Msk
Definition: arm_mpu_v8m.h:37

◆ K_MEM_PARTITION_P_RO_U_NA_NOCACHE

#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE
Value:
#define MPU_MAIR_INDEX_SRAM_NOCACHE
Definition: arm_mpu_v8m.h:110
#define OUTER_SHAREABLE_Msk
Definition: arm_mpu_v8m.h:53

◆ K_MEM_PARTITION_P_RO_U_RO

#define K_MEM_PARTITION_P_RO_U_RO
Value:
#define P_RO_U_RO_Msk
Definition: arm_mpu_v8m.h:40

◆ K_MEM_PARTITION_P_RO_U_RO_NOCACHE

#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE

◆ K_MEM_PARTITION_P_RW_U_NA

#define K_MEM_PARTITION_P_RW_U_NA

◆ K_MEM_PARTITION_P_RW_U_NA_NOCACHE

#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE

◆ K_MEM_PARTITION_P_RW_U_RW

#define K_MEM_PARTITION_P_RW_U_RW

◆ K_MEM_PARTITION_P_RW_U_RW_NOCACHE

#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE

◆ K_MEM_PARTITION_P_RWX_U_RWX

#define K_MEM_PARTITION_P_RWX_U_RWX

◆ K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE

#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE

◆ K_MEM_PARTITION_P_RX_U_RX

#define K_MEM_PARTITION_P_RX_U_RX

◆ K_MEM_PARTITION_P_RX_U_RX_NOCACHE

#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE

◆ MPU_CACHE_ATTRIBUTES_FLASH

#define MPU_CACHE_ATTRIBUTES_FLASH    NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS

◆ MPU_CACHE_ATTRIBUTES_SRAM

#define MPU_CACHE_ATTRIBUTES_SRAM    NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS

◆ MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE

#define MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE    NORMAL_OUTER_INNER_NON_CACHEABLE

◆ MPU_MAIR_ATTR_FLASH

#define MPU_MAIR_ATTR_FLASH   MPU_CACHE_ATTRIBUTES_FLASH

◆ MPU_MAIR_ATTR_SRAM

#define MPU_MAIR_ATTR_SRAM   MPU_CACHE_ATTRIBUTES_SRAM

◆ MPU_MAIR_ATTR_SRAM_NOCACHE

#define MPU_MAIR_ATTR_SRAM_NOCACHE   MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE

◆ MPU_MAIR_INDEX_FLASH

#define MPU_MAIR_INDEX_FLASH   0

◆ MPU_MAIR_INDEX_SRAM

#define MPU_MAIR_INDEX_SRAM   1

◆ MPU_MAIR_INDEX_SRAM_NOCACHE

#define MPU_MAIR_INDEX_SRAM_NOCACHE   2

◆ NON_SHAREABLE

#define NON_SHAREABLE   0x0

◆ NON_SHAREABLE_Msk

#define NON_SHAREABLE_Msk    ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)

◆ NORMAL_I_NON_C

#define NORMAL_I_NON_C   0x04 /* Normal, Inner Non-Cacheable */

◆ NORMAL_I_WB_NT

#define NORMAL_I_WB_NT   0x0C /* Normal, Inner Write-back non-transient */

◆ NORMAL_I_WT_NT

#define NORMAL_I_WT_NT   0x08 /* Normal, Inner Write-through non-transient */

◆ NORMAL_O_NON_C

#define NORMAL_O_NON_C   0x40 /* Normal, Outer Non-Cacheable */

◆ NORMAL_O_WB_NT

#define NORMAL_O_WB_NT   0xC0 /* Normal, Outer Write-back non-transient */

◆ NORMAL_O_WT_NT

#define NORMAL_O_WT_NT   0x80 /* Normal, Outer Write-through non-transient */

◆ NORMAL_OUTER_INNER_NON_CACHEABLE

#define NORMAL_OUTER_INNER_NON_CACHEABLE
Value:
| \
#define R_NON_W_NON
Definition: arm_mpu_v8m.h:67
#define NORMAL_I_NON_C
Definition: arm_mpu_v8m.h:79
#define NORMAL_O_NON_C
Definition: arm_mpu_v8m.h:75

◆ NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS

#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS
Value:
| \
#define R_ALLOC_W_ALLOC
Definition: arm_mpu_v8m.h:70
#define NORMAL_I_WB_NT
Definition: arm_mpu_v8m.h:78
#define NORMAL_O_WB_NT
Definition: arm_mpu_v8m.h:74

◆ NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS

#define NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS
Value:
| \
#define NORMAL_I_WT_NT
Definition: arm_mpu_v8m.h:77
#define NORMAL_O_WT_NT
Definition: arm_mpu_v8m.h:73
#define R_ALLOC_W_NON
Definition: arm_mpu_v8m.h:69

◆ NOT_EXEC

#define NOT_EXEC   MPU_RBAR_XN_Msk

◆ OUTER_SHAREABLE

#define OUTER_SHAREABLE   0x2

◆ OUTER_SHAREABLE_Msk

#define OUTER_SHAREABLE_Msk    ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)

◆ P_RO_U_NA

#define P_RO_U_NA   0x2

◆ P_RO_U_NA_Msk

#define P_RO_U_NA_Msk   ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

◆ P_RO_U_RO

#define P_RO_U_RO   0x3

◆ P_RO_U_RO_Msk

#define P_RO_U_RO_Msk   ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

◆ P_RW_U_NA

#define P_RW_U_NA   0x0

◆ P_RW_U_NA_Msk

#define P_RW_U_NA_Msk   ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

◆ P_RW_U_RW

#define P_RW_U_RW   0x1

◆ P_RW_U_RW_Msk

#define P_RW_U_RW_Msk   ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

◆ R_ALLOC_W_ALLOC

#define R_ALLOC_W_ALLOC   0x3 /* Allocate Read/Write */

◆ R_ALLOC_W_NON

#define R_ALLOC_W_NON   0x2 /* Allocate Read, Do not allocate Write */

◆ R_NON_W_ALLOC

#define R_NON_W_ALLOC   0x1 /* Do not allocate Read, Allocate Write */

◆ R_NON_W_NON

#define R_NON_W_NON   0x0 /* Do not allocate Read/Write */

◆ REGION_FLASH_ATTR

#define REGION_FLASH_ATTR (   base,
  size 
)
Value:
{\
.rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_FLASH, \
.r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
}
#define RO_Msk
Definition: arm_mpu_v8m.h:43
#define NON_SHAREABLE_Msk
Definition: arm_mpu_v8m.h:50
#define MPU_MAIR_INDEX_FLASH
Definition: arm_mpu_v8m.h:106
#define REGION_LIMIT_ADDR(base, size)
Definition: arm_mpu_v8m.h:60

◆ REGION_LIMIT_ADDR

#define REGION_LIMIT_ADDR (   base,
  size 
)     (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk)

◆ REGION_RAM_ATTR

#define REGION_RAM_ATTR (   base,
  size 
)
Value:
{\
.rbar = NOT_EXEC | \
P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
/* Cache-ability */ \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
.r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
}

◆ RO

#define RO   0x3

◆ RO_Msk

#define RO_Msk   ((RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

Typedef Documentation

◆ arm_mpu_region_attr_t