arm_mpu.h File Reference

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Data Structures
struct	arm_mpu_region_attr
struct	arm_mpu_region
struct	arm_mpu_config

Macros
#define	MPU_IR_REGION_Msk   (0xFFU)
#define	MPU_RBAR_BASE_Pos   6U
#define	MPU_RBAR_BASE_Msk   (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos)
#define	MPU_RBAR_SH_Pos   4U
#define	MPU_RBAR_SH_Msk   (0x3UL << MPU_RBAR_SH_Pos)
#define	MPU_RBAR_AP_Pos   2U
#define	MPU_RBAR_AP_Msk   (0x3UL << MPU_RBAR_AP_Pos)
#define	MPU_RBAR_XN_Pos   1U
#define	MPU_RBAR_XN_Msk   (0x1UL << MPU_RBAR_XN_Pos)
#define	MPU_RLAR_LIMIT_Pos   6U
#define	MPU_RLAR_LIMIT_Msk   (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos)
#define	MPU_RLAR_AttrIndx_Pos   1U
#define	MPU_RLAR_AttrIndx_Msk   (0x7UL << MPU_RLAR_AttrIndx_Pos)
#define	MPU_RLAR_EN_Msk   (0x1UL)
#define	NOT_EXEC   MPU_RBAR_XN_Msk /* PRBAR_EL1 */
#define	P_RW_U_NA   0x0U
#define	P_RW_U_NA_Msk   ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
#define	P_RW_U_RW   0x1U
#define	P_RW_U_RW_Msk   ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
#define	P_RO_U_NA   0x2U
#define	P_RO_U_NA_Msk   ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
#define	P_RO_U_RO   0x3U
#define	P_RO_U_RO_Msk   ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
#define	NON_SHAREABLE   0x0U
#define	NON_SHAREABLE_Msk    ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
#define	OUTER_SHAREABLE   0x2U
#define	OUTER_SHAREABLE_Msk    ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
#define	INNER_SHAREABLE   0x3U
#define	INNER_SHAREABLE_Msk    ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
#define	DEVICE_nGnRnE   0x0U
#define	DEVICE_nGnRE   0x4U
#define	DEVICE_nGRE   0x8U
#define	DEVICE_GRE   0xCU
#define	R_NON_W_NON   0x0U /* Do not allocate Read/Write */
#define	R_NON_W_ALLOC   0x1U /* Do not allocate Read, Allocate Write */
#define	R_ALLOC_W_NON   0x2U /* Allocate Read, Do not allocate Write */
#define	R_ALLOC_W_ALLOC   0x3U /* Allocate Read/Write */
#define	NORMAL_O_WT_NT   0x80U /* Normal, Outer Write-through non-transient */
#define	NORMAL_O_WB_NT   0xC0U /* Normal, Outer Write-back non-transient */
#define	NORMAL_O_NON_C   0x40U /* Normal, Outer Non-Cacheable */
#define	NORMAL_I_WT_NT   0x08U /* Normal, Inner Write-through non-transient */
#define	NORMAL_I_WB_NT   0x0CU /* Normal, Inner Write-back non-transient */
#define	NORMAL_I_NON_C   0x04U /* Normal, Inner Non-Cacheable */
#define	MPU_MAIR_INDEX_DEVICE   0U
#define	MPU_MAIR_ATTR_DEVICE   (DEVICE_nGnRnE)
#define	MPU_MAIR_INDEX_FLASH   1U
#define	MPU_MAIR_ATTR_FLASH
#define	MPU_MAIR_INDEX_SRAM   2U
#define	MPU_MAIR_ATTR_SRAM
#define	MPU_MAIR_INDEX_SRAM_NOCACHE   3U
#define	MPU_MAIR_ATTR_SRAM_NOCACHE
#define	MPU_MAIR_ATTRS
#define	REGION_DEVICE_ATTR
#define	REGION_RAM_ATTR
#define	REGION_RAM_TEXT_ATTR
#define	REGION_RAM_RO_ATTR
#define	REGION_FLASH_ATTR
#define	MPU_REGION_ENTRY(_name, _base, _limit, _attr)

Variables
const struct arm_mpu_config	mpu_config

Macro Definition Documentation

DEVICE_GRE

#define DEVICE_GRE   0xCU

DEVICE_nGnRE

#define DEVICE_nGnRE   0x4U

DEVICE_nGnRnE

#define DEVICE_nGnRnE   0x0U

DEVICE_nGRE

#define DEVICE_nGRE   0x8U

INNER_SHAREABLE

#define INNER_SHAREABLE   0x3U

INNER_SHAREABLE_Msk

#define INNER_SHAREABLE_Msk    ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)

MPU_IR_REGION_Msk

#define MPU_IR_REGION_Msk   (0xFFU)

MPU_MAIR_ATTR_DEVICE

#define MPU_MAIR_ATTR_DEVICE   (DEVICE_nGnRnE)

MPU_MAIR_ATTR_FLASH

#define MPU_MAIR_ATTR_FLASH

Value:

        ((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) |      \
         (NORMAL_I_WT_NT | R_ALLOC_W_NON))

MPU_MAIR_ATTR_SRAM

#define MPU_MAIR_ATTR_SRAM

Value:

        ((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) |    \
         (NORMAL_I_WB_NT | R_ALLOC_W_ALLOC))

MPU_MAIR_ATTR_SRAM_NOCACHE

#define MPU_MAIR_ATTR_SRAM_NOCACHE

Value:

        ((NORMAL_O_NON_C | (R_NON_W_NON << 4)) |        \
         (NORMAL_I_NON_C | R_NON_W_NON))

MPU_MAIR_ATTRS

#define MPU_MAIR_ATTRS

Value:

        ((MPU_MAIR_ATTR_DEVICE << (MPU_MAIR_INDEX_DEVICE * 8)) | \
         (MPU_MAIR_ATTR_FLASH << (MPU_MAIR_INDEX_FLASH * 8)) |   \
         (MPU_MAIR_ATTR_SRAM << (MPU_MAIR_INDEX_SRAM * 8)) |     \
         (MPU_MAIR_ATTR_SRAM_NOCACHE << (MPU_MAIR_INDEX_SRAM_NOCACHE * 8)))

MPU_MAIR_INDEX_DEVICE

#define MPU_MAIR_INDEX_DEVICE   0U

MPU_MAIR_INDEX_FLASH

#define MPU_MAIR_INDEX_FLASH   1U

MPU_MAIR_INDEX_SRAM

#define MPU_MAIR_INDEX_SRAM   2U

MPU_MAIR_INDEX_SRAM_NOCACHE

#define MPU_MAIR_INDEX_SRAM_NOCACHE   3U

MPU_RBAR_AP_Msk

#define MPU_RBAR_AP_Msk   (0x3UL << MPU_RBAR_AP_Pos)

MPU_RBAR_AP_Pos

#define MPU_RBAR_AP_Pos   2U

MPU_RBAR_BASE_Msk

#define MPU_RBAR_BASE_Msk   (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos)

MPU_RBAR_BASE_Pos

#define MPU_RBAR_BASE_Pos   6U

MPU_RBAR_SH_Msk

#define MPU_RBAR_SH_Msk   (0x3UL << MPU_RBAR_SH_Pos)

MPU_RBAR_SH_Pos

#define MPU_RBAR_SH_Pos   4U

MPU_RBAR_XN_Msk

#define MPU_RBAR_XN_Msk   (0x1UL << MPU_RBAR_XN_Pos)

MPU_RBAR_XN_Pos

#define MPU_RBAR_XN_Pos   1U

MPU_REGION_ENTRY

#define MPU_REGION_ENTRY	(		_name,
			_base,
			_limit,
			_attr
	)

Value:

        {                                             \
                .name = _name,                        \
                .base = _base,                        \
                .limit = _limit,                      \
                .attr = _attr,                        \
        }

MPU_RLAR_AttrIndx_Msk

#define MPU_RLAR_AttrIndx_Msk   (0x7UL << MPU_RLAR_AttrIndx_Pos)

MPU_RLAR_AttrIndx_Pos

#define MPU_RLAR_AttrIndx_Pos   1U

MPU_RLAR_EN_Msk

#define MPU_RLAR_EN_Msk   (0x1UL)

MPU_RLAR_LIMIT_Msk

#define MPU_RLAR_LIMIT_Msk   (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos)

MPU_RLAR_LIMIT_Pos

#define MPU_RLAR_LIMIT_Pos   6U

NON_SHAREABLE

#define NON_SHAREABLE   0x0U

NON_SHAREABLE_Msk

#define NON_SHAREABLE_Msk    ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)

NORMAL_I_NON_C

#define NORMAL_I_NON_C   0x04U /* Normal, Inner Non-Cacheable */

NORMAL_I_WB_NT

#define NORMAL_I_WB_NT   0x0CU /* Normal, Inner Write-back non-transient */

NORMAL_I_WT_NT

#define NORMAL_I_WT_NT   0x08U /* Normal, Inner Write-through non-transient */

NORMAL_O_NON_C

#define NORMAL_O_NON_C   0x40U /* Normal, Outer Non-Cacheable */

NORMAL_O_WB_NT

#define NORMAL_O_WB_NT   0xC0U /* Normal, Outer Write-back non-transient */

NORMAL_O_WT_NT

#define NORMAL_O_WT_NT   0x80U /* Normal, Outer Write-through non-transient */

NOT_EXEC

#define NOT_EXEC   MPU_RBAR_XN_Msk /* PRBAR_EL1 */

OUTER_SHAREABLE

#define OUTER_SHAREABLE   0x2U

OUTER_SHAREABLE_Msk

#define OUTER_SHAREABLE_Msk    ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)

P_RO_U_NA

#define P_RO_U_NA   0x2U

P_RO_U_NA_Msk

#define P_RO_U_NA_Msk   ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

P_RO_U_RO

#define P_RO_U_RO   0x3U

P_RO_U_RO_Msk

#define P_RO_U_RO_Msk   ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

P_RW_U_NA

#define P_RW_U_NA   0x0U

P_RW_U_NA_Msk

#define P_RW_U_NA_Msk   ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

P_RW_U_RW

#define P_RW_U_RW   0x1U

P_RW_U_RW_Msk

#define P_RW_U_RW_Msk   ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)

R_ALLOC_W_ALLOC

#define R_ALLOC_W_ALLOC   0x3U /* Allocate Read/Write */

R_ALLOC_W_NON

#define R_ALLOC_W_NON   0x2U /* Allocate Read, Do not allocate Write */

R_NON_W_ALLOC

#define R_NON_W_ALLOC   0x1U /* Do not allocate Read, Allocate Write */

R_NON_W_NON

#define R_NON_W_NON   0x0U /* Do not allocate Read/Write */

REGION_DEVICE_ATTR

#define REGION_DEVICE_ATTR

Value:

        {                                                             \
                /* AP, XN, SH */                                      \
                .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
                /* Cache-ability */                                   \
                .mair_idx = MPU_MAIR_INDEX_DEVICE,                    \
        }

REGION_FLASH_ATTR

#define REGION_FLASH_ATTR

Value:

        {                                                                   \
                .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
                /* Cache-ability */                                         \
                .mair_idx = MPU_MAIR_INDEX_FLASH,                           \
        }

REGION_RAM_ATTR

#define REGION_RAM_ATTR

Value:

        {                                                             \
                /* AP, XN, SH */                                      \
                .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
                /* Cache-ability */                                   \
                .mair_idx = MPU_MAIR_INDEX_SRAM,                      \
        }

REGION_RAM_RO_ATTR

#define REGION_RAM_RO_ATTR

Value:

        {                                                             \
                /* AP, XN, SH */                                      \
                .rbar = NOT_EXEC | P_RO_U_NA_Msk | NON_SHAREABLE_Msk, \
                /* Cache-ability */                                   \
                .mair_idx = MPU_MAIR_INDEX_SRAM,                      \
        }

REGION_RAM_TEXT_ATTR

#define REGION_RAM_TEXT_ATTR

Value:

        {                                                  \
                /* AP, XN, SH */                           \
                .rbar = P_RO_U_NA_Msk | NON_SHAREABLE_Msk, \
                /* Cache-ability */                        \
                .mair_idx = MPU_MAIR_INDEX_SRAM,           \
        }

Variable Documentation

mpu_config

const struct arm_mpu_config mpu_config

extern