cap.h File Reference

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Macros
#define	PCI_CAP_ID_NULL   0x00U /* Null Capability */
#define	PCI_CAP_ID_PM   0x01U /* Power Management */
#define	PCI_CAP_ID_AGP   0x02U /* Accelerated Graphics Port */
#define	PCI_CAP_ID_VPD   0x03U /* Vital Product Data */
#define	PCI_CAP_ID_SLOTID   0x04U /* Slot Identification */
#define	PCI_CAP_ID_MSI   0x05U /* Message Signalled Interrupts */
#define	PCI_CAP_ID_CHSWP   0x06U /* CompactPCI HotSwap */
#define	PCI_CAP_ID_PCIX   0x07U /* PCI-X */
#define	PCI_CAP_ID_HT   0x08U /* HyperTransport */
#define	PCI_CAP_ID_VNDR   0x09U /* Vendor-Specific */
#define	PCI_CAP_ID_DBG   0x0AU /* Debug port */
#define	PCI_CAP_ID_CCRC   0x0BU /* CompactPCI Central Resource Control */
#define	PCI_CAP_ID_SHPC   0x0CU /* PCI Standard Hot-Plug Controller */
#define	PCI_CAP_ID_SSVID   0x0DU /* Bridge subsystem vendor/device ID */
#define	PCI_CAP_ID_AGP3   0x0EU /* AGP 8x */
#define	PCI_CAP_ID_SECDEV   0x0FU /* Secure Device */
#define	PCI_CAP_ID_EXP   0x10U /* PCI Express */
#define	PCI_CAP_ID_MSIX   0x11U /* MSI-X */
#define	PCI_CAP_ID_SATA   0x12U /* Serial ATA Data/Index Configuration */
#define	PCI_CAP_ID_AF   0x13U /* PCI Advanced Features */
#define	PCI_CAP_ID_EA   0x14U /* PCI Enhanced Allocation */
#define	PCI_CAP_ID_FPB   0x14U /* Flattening Portal Bridge */
#define	PCI_EXT_CAP_ID_NULL   0x0000U /* Null Capability */
#define	PCI_EXT_CAP_ID_ERR   0x0001U /* Advanced Error Reporting */
#define	PCI_EXT_CAP_ID_VC   0x0002U /* Virtual Channel when no MFVC */
#define	PCI_EXT_CAP_ID_DSN   0x0003U /* Device Serial Number */
#define	PCI_EXT_CAP_ID_PWR   0x0004U /* Power Budgeting */
#define	PCI_EXT_CAP_ID_RCLD   0x0005U /* Root Complex Link Declaration */
#define	PCI_EXT_CAP_ID_RCILC   0x0006U /* Root Complex Internal Link Control */
#define	PCI_EXT_CAP_ID_RCEC   0x0007U /* Root Complex Event Collector Endpoint Association */
#define	PCI_EXT_CAP_ID_MFVC   0x0008U /* Multi-Function VC Capability */
#define	PCI_EXT_CAP_ID_MFVC_VC   0x0009U /* Virtual Channel used with MFVC */
#define	PCI_EXT_CAP_ID_RCRB   0x000AU /* Root Complex Register Block */
#define	PCI_EXT_CAP_ID_VNDR   0x000BU /* Vendor-Specific Extended Capability */
#define	PCI_EXT_CAP_ID_CAC   0x000CU /* Config Access Correlation - obsolete */
#define	PCI_EXT_CAP_ID_ACS   0x000DU /* Access Control Services */
#define	PCI_EXT_CAP_ID_ARI   0x000EU /* Alternate Routing-ID Interpretation */
#define	PCI_EXT_CAP_ID_ATS   0x000FU /* Address Translation Services */
#define	PCI_EXT_CAP_ID_SRIOV   0x0010U /* Single Root I/O Virtualization */
#define	PCI_EXT_CAP_ID_MRIOV   0x0011U /* Multi Root I/O Virtualization */
#define	PCI_EXT_CAP_ID_MCAST   0x0012U /* Multicast */
#define	PCI_EXT_CAP_ID_PRI   0x0013U /* Page Request Interface */
#define	PCI_EXT_CAP_ID_AMD_XXX   0x0014U /* Reserved for AMD */
#define	PCI_EXT_CAP_ID_REBAR   0x0015U /* Resizable BAR */
#define	PCI_EXT_CAP_ID_DPA   0x0016U /* Dynamic Power Allocation */
#define	PCI_EXT_CAP_ID_TPH   0x0017U /* TPH Requester */
#define	PCI_EXT_CAP_ID_LTR   0x0018U /* Latency Tolerance Reporting */
#define	PCI_EXT_CAP_ID_SECPCI   0x0019U /* Secondary PCIe Capability */
#define	PCI_EXT_CAP_ID_PMUX   0x001AU /* Protocol Multiplexing */
#define	PCI_EXT_CAP_ID_PASID   0x001BU /* Process Address Space ID */
#define	PCI_EXT_CAP_ID_DPC   0x001DU /* DPC: Downstream Port Containment */
#define	PCI_EXT_CAP_ID_L1SS   0x001EU /* L1 PM Substates */
#define	PCI_EXT_CAP_ID_PTM   0x001FU /* Precision Time Measurement */
#define	PCI_EXT_CAP_ID_DVSEC   0x0023U /* Designated Vendor-Specific Extended Capability */
#define	PCI_EXT_CAP_ID_DLF   0x0025U /* Data Link Feature */
#define	PCI_EXT_CAP_ID_PL_16GT   0x0026U /* Physical Layer 16.0 GT/s */
#define	PCI_EXT_CAP_ID_LMR   0x0027U /* Lane Margining at the Receiver */
#define	PCI_EXT_CAP_ID_HID   0x0028U /* Hierarchy ID */
#define	PCI_EXT_CAP_ID_NPEM   0x0029U /* Native PCIe Enclosure Management */
#define	PCI_EXT_CAP_ID_PL_32GT   0x002AU /* Physical Layer 32.0 GT/s */
#define	PCI_EXT_CAP_ID_AP   0x002BU /* Alternate Protocol */
#define	PCI_EXT_CAP_ID_SFI   0x002CU /* System Firmware Intermediary */

Macro Definition Documentation

PCI_CAP_ID_AF

#define PCI_CAP_ID_AF   0x13U /* PCI Advanced Features */

PCI_CAP_ID_AGP

#define PCI_CAP_ID_AGP   0x02U /* Accelerated Graphics Port */

PCI_CAP_ID_AGP3

#define PCI_CAP_ID_AGP3   0x0EU /* AGP 8x */

PCI_CAP_ID_CCRC

#define PCI_CAP_ID_CCRC   0x0BU /* CompactPCI Central Resource Control */

PCI_CAP_ID_CHSWP

#define PCI_CAP_ID_CHSWP   0x06U /* CompactPCI HotSwap */

PCI_CAP_ID_DBG

#define PCI_CAP_ID_DBG   0x0AU /* Debug port */

PCI_CAP_ID_EA

#define PCI_CAP_ID_EA   0x14U /* PCI Enhanced Allocation */

PCI_CAP_ID_EXP

#define PCI_CAP_ID_EXP   0x10U /* PCI Express */

PCI_CAP_ID_FPB

#define PCI_CAP_ID_FPB   0x14U /* Flattening Portal Bridge */

PCI_CAP_ID_HT

#define PCI_CAP_ID_HT   0x08U /* HyperTransport */

PCI_CAP_ID_MSI

#define PCI_CAP_ID_MSI   0x05U /* Message Signalled Interrupts */

PCI_CAP_ID_MSIX

#define PCI_CAP_ID_MSIX   0x11U /* MSI-X */

PCI_CAP_ID_NULL

#define PCI_CAP_ID_NULL   0x00U /* Null Capability */

PCI_CAP_ID_PCIX

#define PCI_CAP_ID_PCIX   0x07U /* PCI-X */

PCI_CAP_ID_PM

#define PCI_CAP_ID_PM   0x01U /* Power Management */

PCI_CAP_ID_SATA

#define PCI_CAP_ID_SATA   0x12U /* Serial ATA Data/Index Configuration */

PCI_CAP_ID_SECDEV

#define PCI_CAP_ID_SECDEV   0x0FU /* Secure Device */

PCI_CAP_ID_SHPC

#define PCI_CAP_ID_SHPC   0x0CU /* PCI Standard Hot-Plug Controller */

PCI_CAP_ID_SLOTID

#define PCI_CAP_ID_SLOTID   0x04U /* Slot Identification */

PCI_CAP_ID_SSVID

#define PCI_CAP_ID_SSVID   0x0DU /* Bridge subsystem vendor/device ID */

PCI_CAP_ID_VNDR

#define PCI_CAP_ID_VNDR   0x09U /* Vendor-Specific */

PCI_CAP_ID_VPD

#define PCI_CAP_ID_VPD   0x03U /* Vital Product Data */

PCI_EXT_CAP_ID_ACS

#define PCI_EXT_CAP_ID_ACS   0x000DU /* Access Control Services */

PCI_EXT_CAP_ID_AMD_XXX

#define PCI_EXT_CAP_ID_AMD_XXX   0x0014U /* Reserved for AMD */

PCI_EXT_CAP_ID_AP

#define PCI_EXT_CAP_ID_AP   0x002BU /* Alternate Protocol */

PCI_EXT_CAP_ID_ARI

#define PCI_EXT_CAP_ID_ARI   0x000EU /* Alternate Routing-ID Interpretation */

PCI_EXT_CAP_ID_ATS

#define PCI_EXT_CAP_ID_ATS   0x000FU /* Address Translation Services */

PCI_EXT_CAP_ID_CAC

#define PCI_EXT_CAP_ID_CAC   0x000CU /* Config Access Correlation - obsolete */

PCI_EXT_CAP_ID_DLF

#define PCI_EXT_CAP_ID_DLF   0x0025U /* Data Link Feature */

PCI_EXT_CAP_ID_DPA

#define PCI_EXT_CAP_ID_DPA   0x0016U /* Dynamic Power Allocation */

PCI_EXT_CAP_ID_DPC

#define PCI_EXT_CAP_ID_DPC   0x001DU /* DPC: Downstream Port Containment */

PCI_EXT_CAP_ID_DSN

#define PCI_EXT_CAP_ID_DSN   0x0003U /* Device Serial Number */

PCI_EXT_CAP_ID_DVSEC

#define PCI_EXT_CAP_ID_DVSEC   0x0023U /* Designated Vendor-Specific Extended Capability */

PCI_EXT_CAP_ID_ERR

#define PCI_EXT_CAP_ID_ERR   0x0001U /* Advanced Error Reporting */

PCI_EXT_CAP_ID_HID

#define PCI_EXT_CAP_ID_HID   0x0028U /* Hierarchy ID */

PCI_EXT_CAP_ID_L1SS

#define PCI_EXT_CAP_ID_L1SS   0x001EU /* L1 PM Substates */

PCI_EXT_CAP_ID_LMR

#define PCI_EXT_CAP_ID_LMR   0x0027U /* Lane Margining at the Receiver */

PCI_EXT_CAP_ID_LTR

#define PCI_EXT_CAP_ID_LTR   0x0018U /* Latency Tolerance Reporting */

PCI_EXT_CAP_ID_MCAST

#define PCI_EXT_CAP_ID_MCAST   0x0012U /* Multicast */

PCI_EXT_CAP_ID_MFVC

#define PCI_EXT_CAP_ID_MFVC   0x0008U /* Multi-Function VC Capability */

PCI_EXT_CAP_ID_MFVC_VC

#define PCI_EXT_CAP_ID_MFVC_VC   0x0009U /* Virtual Channel used with MFVC */

PCI_EXT_CAP_ID_MRIOV

#define PCI_EXT_CAP_ID_MRIOV   0x0011U /* Multi Root I/O Virtualization */

PCI_EXT_CAP_ID_NPEM

#define PCI_EXT_CAP_ID_NPEM   0x0029U /* Native PCIe Enclosure Management */

PCI_EXT_CAP_ID_NULL

#define PCI_EXT_CAP_ID_NULL   0x0000U /* Null Capability */

PCI_EXT_CAP_ID_PASID

#define PCI_EXT_CAP_ID_PASID   0x001BU /* Process Address Space ID */

PCI_EXT_CAP_ID_PL_16GT

#define PCI_EXT_CAP_ID_PL_16GT   0x0026U /* Physical Layer 16.0 GT/s */

PCI_EXT_CAP_ID_PL_32GT

#define PCI_EXT_CAP_ID_PL_32GT   0x002AU /* Physical Layer 32.0 GT/s */

PCI_EXT_CAP_ID_PMUX

#define PCI_EXT_CAP_ID_PMUX   0x001AU /* Protocol Multiplexing */

PCI_EXT_CAP_ID_PRI

#define PCI_EXT_CAP_ID_PRI   0x0013U /* Page Request Interface */

PCI_EXT_CAP_ID_PTM

#define PCI_EXT_CAP_ID_PTM   0x001FU /* Precision Time Measurement */

PCI_EXT_CAP_ID_PWR

#define PCI_EXT_CAP_ID_PWR   0x0004U /* Power Budgeting */

PCI_EXT_CAP_ID_RCEC

#define PCI_EXT_CAP_ID_RCEC   0x0007U /* Root Complex Event Collector Endpoint Association */

PCI_EXT_CAP_ID_RCILC

#define PCI_EXT_CAP_ID_RCILC   0x0006U /* Root Complex Internal Link Control */

PCI_EXT_CAP_ID_RCLD

#define PCI_EXT_CAP_ID_RCLD   0x0005U /* Root Complex Link Declaration */

PCI_EXT_CAP_ID_RCRB

#define PCI_EXT_CAP_ID_RCRB   0x000AU /* Root Complex Register Block */

PCI_EXT_CAP_ID_REBAR

#define PCI_EXT_CAP_ID_REBAR   0x0015U /* Resizable BAR */

PCI_EXT_CAP_ID_SECPCI

#define PCI_EXT_CAP_ID_SECPCI   0x0019U /* Secondary PCIe Capability */

PCI_EXT_CAP_ID_SFI

#define PCI_EXT_CAP_ID_SFI   0x002CU /* System Firmware Intermediary */

PCI_EXT_CAP_ID_SRIOV

#define PCI_EXT_CAP_ID_SRIOV   0x0010U /* Single Root I/O Virtualization */

PCI_EXT_CAP_ID_TPH

#define PCI_EXT_CAP_ID_TPH   0x0017U /* TPH Requester */

PCI_EXT_CAP_ID_VC

#define PCI_EXT_CAP_ID_VC   0x0002U /* Virtual Channel when no MFVC */

PCI_EXT_CAP_ID_VNDR

#define PCI_EXT_CAP_ID_VNDR   0x000BU /* Vendor-Specific Extended Capability */