16#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ARCH_H_
17#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ARCH_H_
23#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
36#ifdef CONFIG_CPU_CORTEX_M
40#elif defined(CONFIG_CPU_CORTEX_R)
57#ifdef CONFIG_STACK_ALIGN_DOUBLE_WORD
58#define ARCH_STACK_PTR_ALIGN 8
60#define ARCH_STACK_PTR_ALIGN 4
72#if defined(CONFIG_USERSPACE)
73#define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
75#define Z_THREAD_MIN_STACK_ALIGN ARCH_STACK_PTR_ALIGN
118#if defined(CONFIG_MPU_STACK_GUARD)
119#define MPU_GUARD_ALIGN_AND_SIZE CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
121#define MPU_GUARD_ALIGN_AND_SIZE 0
134#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) \
135 && defined(CONFIG_MPU_STACK_GUARD)
136#define MPU_GUARD_ALIGN_AND_SIZE_FLOAT CONFIG_MPU_STACK_GUARD_MIN_SIZE_FLOAT
138#define MPU_GUARD_ALIGN_AND_SIZE_FLOAT 0
148#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
149#define Z_MPU_GUARD_ALIGN (MAX(MPU_GUARD_ALIGN_AND_SIZE, \
150 MPU_GUARD_ALIGN_AND_SIZE_FLOAT))
152#define Z_MPU_GUARD_ALIGN MPU_GUARD_ALIGN_AND_SIZE
155#if defined(CONFIG_USERSPACE) && \
156 defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
162#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_POW2_CEIL(size)
163#define ARCH_THREAD_STACK_SIZE_ADJUST(size) Z_POW2_CEIL(size)
165#define ARCH_THREAD_STACK_OBJ_ALIGN(size) MAX(Z_THREAD_MIN_STACK_ALIGN, \
167#ifdef CONFIG_USERSPACE
168#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
169 ROUND_UP(size, CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
173#ifdef CONFIG_MPU_STACK_GUARD
177#define ARCH_KERNEL_STACK_RESERVED MPU_GUARD_ALIGN_AND_SIZE
178#define ARCH_KERNEL_STACK_OBJ_ALIGN Z_MPU_GUARD_ALIGN
182#define ARCH_THREAD_STACK_RESERVED 0
186#ifdef CONFIG_CPU_HAS_ARM_MPU
189#ifdef CONFIG_CPU_HAS_NXP_MPU
ARM AArch32 public interrupt handling.
Per-arch thread definition.
ARM AArch32 public error handling.
ARM AArch32 public exception handling.
ARM AArch32 public kernel miscellaneous.
ARM AArch32 NMI routines.