Macros
#define	SCTRL_MPU_ENABLE (1 << 0)

#define	MODE_USR 0x10

#define	MODE_FIQ 0x11

#define	MODE_IRQ 0x12

#define	MODE_SVC 0x13

#define	MODE_ABT 0x17

#define	MODE_UND 0x1b

#define	MODE_SYS 0x1f

#define	MODE_MASK 0x1f

#define	A_BIT (1 << 8)

#define	I_BIT (1 << 7)

#define	F_BIT (1 << 6)

#define	T_BIT (1 << 5)

#define	HIVECS (1 << 13)

#define	CPACR_NA (0U)

#define	CPACR_FA (3U)

#define	CPACR_CP10(r) (r << 20)

#define	CPACR_CP11(r) (r << 22)

#define	FPEXC_EN (1 << 30)

#define	DFSR_DOMAIN_SHIFT (4)

#define	DFSR_DOMAIN_MASK (0xf)

#define	DFSR_FAULT_4_MASK (1 << 10)

#define	DFSR_WRITE_MASK (1 << 11)

#define	DFSR_AXI_SLAVE_MASK (1 << 12)

Macro Definition Documentation

◆ A_BIT

#define A_BIT (1 << 8)

◆ CPACR_CP10

#define CPACR_CP10 ( r ) (r << 20)

◆ CPACR_CP11

#define CPACR_CP11 ( r ) (r << 22)

◆ CPACR_FA

#define CPACR_FA (3U)

◆ CPACR_NA

#define CPACR_NA (0U)

◆ DFSR_AXI_SLAVE_MASK

#define DFSR_AXI_SLAVE_MASK (1 << 12)

◆ DFSR_DOMAIN_MASK

#define DFSR_DOMAIN_MASK (0xf)

◆ DFSR_DOMAIN_SHIFT

#define DFSR_DOMAIN_SHIFT (4)

◆ DFSR_FAULT_4_MASK

#define DFSR_FAULT_4_MASK (1 << 10)

◆ DFSR_WRITE_MASK

#define DFSR_WRITE_MASK (1 << 11)

◆ F_BIT

#define F_BIT (1 << 6)

◆ FPEXC_EN

#define FPEXC_EN (1 << 30)

◆ HIVECS

#define HIVECS (1 << 13)

◆ I_BIT

#define I_BIT (1 << 7)

◆ MODE_ABT

#define MODE_ABT 0x17

◆ MODE_FIQ

#define MODE_FIQ 0x11

◆ MODE_IRQ

#define MODE_IRQ 0x12

◆ MODE_MASK

#define MODE_MASK 0x1f

◆ MODE_SVC

#define MODE_SVC 0x13

◆ MODE_SYS

#define MODE_SYS 0x1f

◆ MODE_UND

#define MODE_UND 0x1b

◆ MODE_USR

#define MODE_USR 0x10

◆ SCTRL_MPU_ENABLE

#define SCTRL_MPU_ENABLE (1 << 0)

◆ T_BIT

#define T_BIT (1 << 5)

Macros