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st,stm32l4-pll-clock

Vendor: STMicroelectronics

Description

PLL node binding for STM32L4 and STM32L5 devices

It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
Only main PLL is supported for now.

These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

Each PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLL_P) = f(VCO clock) / PLLP  --> PLLSAI3CLK
  f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48M1CLK
  f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

The PLL output frequency must not exceed 80 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

div-m

int

 
Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
input clock
Valid range: 1 - 8

This property is required.

mul-n

int

 
Main PLL multiplication factor for VCO
Valid range: 8 - 86

This property is required.

div-p

int

 
Main PLL division factor for PLLSAI3CLK

Legal values: 7, 17

div-q

int

 
Main PLL division factor for PLL48M1CLK (48 MHz clock).

Legal values: 2, 4, 6, 8

div-r

int

 
Main PLL division factor for PLLCLK (system clock)

This property is required.

Legal values: 2, 4, 6, 8