This is the documentation for the latest (main) development branch of Zephyr. If you are looking for the documentation of previous releases, use the drop-down menu on the left and select the desired version.

st,stm32f105-pll-clock

Vendor: STMicroelectronics

Description

Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)

Takes one of clk_hse, pll2 or clk_hsi as input clock.
When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
pll2, configurable prescaler is used.

Up to 2 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:

  f(PLLCLK) = f(PLLIN) x PLLMUL       --> SYSCLK (System Clock)
  f(USBCLK) = f(PLLCLK) * 2 / USBPRE  --> USB

  with, depending on the case:
          f(PLLIN) = f(input_clk) / 2       if input_clk = clk_hsi
          f(PLLIN) = f(input_clk) / PREDIV  if input_clk = clk_hse or pll2

The PLL output frequency must not exceed 72 MHz.

Properties

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
#clock-cells	int	Number of items to expect in a Clock specifier This property is required.
mul	int	Main PLL multiplication factor for VCO. Note: For x6.5 multiplier value, please use "mul = <15>;" This property is required. Legal values: 4, 5, 6, 7, 8, 9, 15
prediv	int	Configurable prescaler Valid range: 1 - 16