Zephyr API Documentation  2.7.0-rc2
A Scalable Open Source RTOS
stm32_clock_control.h
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1/*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2016 BayLibre, SAS
4 * Copyright (c) 2017 Linaro Limited.
5 * Copyright (c) 2017 RnDity Sp. z o.o.
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
10#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
11
12#include <drivers/clock_control.h>
13#include <dt-bindings/clock/stm32_clock.h>
14
15/* common clock control device node for all STM32 chips */
16#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
17
18/*
19 * Kconfig to device tree transition for clocks on STM32 targets:
20 *
21 * Following definitions are provided to allow a smooth transition
22 * between Kconfig based to dts based clocks configuration.
23 * These symbols allow to have both configuration schemes used simultaneoulsy
24 * while giving precedence to dts based configuration once available on a
25 * target.
26 * Finally, once all in-tree users are converted to dts based configuration,
27 * we'll be able to generate deprecation warnings for out of tree users of
28 * Kconfig related symbols.
29 */
30
31#if defined(STM32_AHB_PRESCALER) || \
32 defined(CONFIG_CLOCK_STM32_APB1_PRESCALER) || \
33 defined(CONFIG_CLOCK_STM32_APB2_PRESCALER) || \
34 defined(CONFIG_CLOCK_STM32_AHB3_PRESCALER) || \
35 defined(CONFIG_CLOCK_STM32_AHB4_PRESCALER) || \
36 defined(CONFIG_CLOCK_STM32_CPU1_PRESCALER) || \
37 defined(CONFIG_CLOCK_STM32_CPU2_PRESCALER) || \
38 defined(CONFIG_CLOCK_STM32_PLL_M_DIVISOR) || \
39 defined(CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER) || \
40 defined(CONFIG_CLOCK_STM32_PLL_P_DIVISOR) || \
41 defined(CONFIG_CLOCK_STM32_PLL_Q_DIVISOR) || \
42 defined(CONFIG_CLOCK_STM32_PLL_R_DIVISOR) || \
43 defined(CONFIG_CLOCK_STM32_PLL_XTPRE) || \
44 defined(CONFIG_CLOCK_STM32_PLL_MULTIPLIER) || \
45 defined(CONFIG_CLOCK_STM32_PLL_PREDIV1) || \
46 defined(CONFIG_CLOCK_STM32_PLL_PREDIV) || \
47 defined(CONFIG_CLOCK_STM32_PLL_DIVISOR) || \
48 defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL) || \
49 defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI) || \
50 defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE) || \
51 defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI) || \
52 defined(CONFIG_CLOCK_STM32_PLL_SRC_MSI) || \
53 defined(CONFIG_CLOCK_STM32_PLL_SRC_HSI) || \
54 defined(CONFIG_CLOCK_STM32_PLL_SRC_HSE) || \
55 defined(CONFIG_CLOCK_STM32_PLL_SRC_PLL2) || \
56 defined(CONFIG_CLOCK_STM32_LSE) || \
57 defined(CONFIG_CLOCK_STM32_MSI_RANGE) || \
58 defined(CONFIG_CLOCK_STM32_MSI_PLL_MODE) || \
59 defined(CONFIG_CLOCK_STM32_HSE_BYPASS) || \
60 defined(CONFIG_CLOCK_STM32_D1CPRE) || \
61 defined(CONFIG_CLOCK_STM32_HPRE) || \
62 defined(CONFIG_CLOCK_STM32_D2PPRE1) || \
63 defined(CONFIG_CLOCK_STM32_D2PPRE2) || \
64 defined(CONFIG_CLOCK_STM32_D1PPRE) || \
65 defined(CONFIG_CLOCK_STM32_D3PPRE) || \
66 defined(CONFIG_CLOCK_STM32_PLL3_ENABLE) || \
67 defined(CONFIG_CLOCK_STM32_PLL3_M_DIVISOR) || \
68 defined(CONFIG_CLOCK_STM32_PLL3_N_MULTIPLIER) || \
69 defined(CONFIG_CLOCK_STM32_PLL3_P_ENABLE) || \
70 defined(CONFIG_CLOCK_STM32_PLL3_P_DIVISOR) || \
71 defined(CONFIG_CLOCK_STM32_PLL3_Q_ENABLE) || \
72 defined(CONFIG_CLOCK_STM32_PLL3_Q_DIVISOR) || \
73 defined(CONFIG_CLOCK_STM32_PLL3_R_ENABLE) || \
74 defined(CONFIG_CLOCK_STM32_PLL3_R_DIVISOR) || \
75 defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI) || \
76 defined(CONFIG_CLOCK_STM32_HSI_DIVISOR)
77#warning "Deprecated: Please use device tree for STM32 clock_control configuration"
78/*
79 * Use of Kconfig for STM32 clock_control configuration is deprecated.
80 * It is replaced by use of device tree.
81 * For more information, see:
82 * https://github.com/zephyrproject-rtos/zephyr/pull/34120
83 * https://github.com/zephyrproject-rtos/zephyr/pull/34609
84 * https://github.com/zephyrproject-rtos/zephyr/pull/34701
85 * and
86 * https://github.com/zephyrproject-rtos/zephyr/issues/34633
87 */
88#endif
89
90#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), ahb_prescaler) || \
91 DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), ahb_prescaler) || \
92 DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), ahb_prescaler)
93#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
94#else
95#define STM32_AHB_PRESCALER CONFIG_CLOCK_STM32_AHB_PRESCALER
96#endif
97
98#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb1_prescaler) || \
99 DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), apb1_prescaler) || \
100 DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb1_prescaler) || \
101 DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb1_prescaler) || \
102 DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb1_prescaler)
103#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
104#else
105#define STM32_APB1_PRESCALER CONFIG_CLOCK_STM32_APB1_PRESCALER
106#endif
107
108#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb2_prescaler) || \
109 DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb2_prescaler) || \
110 DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb2_prescaler) || \
111 DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb2_prescaler)
112#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
113#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32f0_rcc, okay)
114 /* This should not be defined in F0 binding case */
115#define STM32_APB2_PRESCALER CONFIG_CLOCK_STM32_APB2_PRESCALER
116#endif
117
118#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb3_prescaler)
119#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
120#endif
121
122#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), ahb3_prescaler)
123#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
124#else
125#define STM32_AHB3_PRESCALER CONFIG_CLOCK_STM32_AHB3_PRESCALER
126#endif
127
128#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), ahb4_prescaler)
129#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
130#else
131#define STM32_AHB4_PRESCALER CONFIG_CLOCK_STM32_AHB4_PRESCALER
132#endif
133
134#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), cpu1_prescaler) || \
135 DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), cpu1_prescaler)
136#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
137#else
138#define STM32_CPU1_PRESCALER CONFIG_CLOCK_STM32_CPU1_PRESCALER
139#endif
140
141#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), cpu2_prescaler) || \
142 DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), cpu2_prescaler)
143#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
144#else
145#define STM32_CPU2_PRESCALER CONFIG_CLOCK_STM32_CPU2_PRESCALER
146#endif
147
148#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32h7_rcc, okay) && \
149 DT_NODE_HAS_PROP(DT_NODELABEL(rcc), d1cpre)
150#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
151#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
152#define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
153#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
154#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
155#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
156#else
157#define STM32_D1CPRE CONFIG_CLOCK_STM32_D1CPRE
158#define STM32_HPRE CONFIG_CLOCK_STM32_HPRE
159#define STM32_D2PPRE1 CONFIG_CLOCK_STM32_D2PPRE1
160#define STM32_D2PPRE2 CONFIG_CLOCK_STM32_D2PPRE2
161#define STM32_D1PPRE CONFIG_CLOCK_STM32_D1PPRE
162#define STM32_D3PPRE CONFIG_CLOCK_STM32_D3PPRE
163#endif
164
165#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
166 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
167 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
168 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
169 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
170 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
171 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
172 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
173 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay)
174#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
175#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
176#define STM32_PLL_P_DIVISOR DT_PROP(DT_NODELABEL(pll), div_p)
177#define STM32_PLL_Q_DIVISOR DT_PROP(DT_NODELABEL(pll), div_q)
178#define STM32_PLL_R_DIVISOR DT_PROP(DT_NODELABEL(pll), div_r)
179#else
180#define STM32_PLL_M_DIVISOR CONFIG_CLOCK_STM32_PLL_M_DIVISOR
181#define STM32_PLL_N_MULTIPLIER CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER
182#define STM32_PLL_P_DIVISOR CONFIG_CLOCK_STM32_PLL_P_DIVISOR
183#define STM32_PLL_Q_DIVISOR CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
184#define STM32_PLL_R_DIVISOR CONFIG_CLOCK_STM32_PLL_R_DIVISOR
185#endif
186
187#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay)
188#define STM32_PLL3_ENABLE 1
189#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
190#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
191#define STM32_PLL3_P_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
192#define STM32_PLL3_P_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p)
193#define STM32_PLL3_Q_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
194#define STM32_PLL3_Q_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_q)
195#define STM32_PLL3_R_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
196#define STM32_PLL3_R_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_r)
197#else
198#define STM32_PLL3_ENABLE CONFIG_CLOCK_STM32_PLL3_ENABLE
199#define STM32_PLL3_M_DIVISOR CONFIG_CLOCK_STM32_PLL3_M_DIVISOR
200#define STM32_PLL3_N_MULTIPLIER CONFIG_CLOCK_STM32_PLL3_N_MULTIPLIER
201#define STM32_PLL3_P_ENABLE CONFIG_CLOCK_STM32_PLL3_P_ENABLE
202#define STM32_PLL3_P_DIVISOR CONFIG_CLOCK_STM32_PLL3_P_DIVISOR
203#define STM32_PLL3_Q_ENABLE CONFIG_CLOCK_STM32_PLL3_Q_ENABLE
204#define STM32_PLL3_Q_DIVISOR CONFIG_CLOCK_STM32_PLL3_Q_DIVISOR
205#define STM32_PLL3_R_ENABLE CONFIG_CLOCK_STM32_PLL3_R_ENABLE
206#define STM32_PLL3_R_DIVISOR CONFIG_CLOCK_STM32_PLL3_R_DIVISOR
207#endif
208
209#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
210#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtre)
211#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
212#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
213 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
214 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
215#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
216#define STM32_PLL_PREDIV1 DT_PROP(DT_NODELABEL(pll), prediv)
217/* We don't need to make a disctinction between PREDIV and PREDIV1 in dts */
218/* As PREDIV and PREDIV1 have the same description we can use prop prediv for both */
219#define STM32_PLL_PREDIV STM32_PLL_PREDIV1
220#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
221#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
222#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
223#else
224#define STM32_PLL_XTPRE CONFIG_CLOCK_STM32_PLL_XTPRE
225#define STM32_PLL_MULTIPLIER CONFIG_CLOCK_STM32_PLL_MULTIPLIER
226#define STM32_PLL_PREDIV1 CONFIG_CLOCK_STM32_PLL_PREDIV1
227#define STM32_PLL_PREDIV CONFIG_CLOCK_STM32_PLL_PREDIV
228#define STM32_PLL_DIVISOR CONFIG_CLOCK_STM32_PLL_DIVISOR
229#endif
230
231#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32_rcc, okay) || \
232 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32f0_rcc, okay) || \
233 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32h7_rcc, okay) || \
234 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32u5_rcc, okay) || \
235 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wb_rcc, okay) || \
236 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wl_rcc, okay)) && \
237 DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks)
238#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
239#define STM32_SYSCLK_SRC_PLL DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
240#define STM32_SYSCLK_SRC_HSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
241#define STM32_SYSCLK_SRC_HSE DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
242#define STM32_SYSCLK_SRC_MSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
243#define STM32_SYSCLK_SRC_CSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
244#else
245#define STM32_SYSCLK_SRC_PLL CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
246#define STM32_SYSCLK_SRC_HSI CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI
247#define STM32_SYSCLK_SRC_HSE CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE
248#define STM32_SYSCLK_SRC_MSI CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI
249#define STM32_SYSCLK_SRC_CSI CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI
250#endif
251
252#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
253 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay) || \
254 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
255 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay) || \
256 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
257 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
258 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
259 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
260 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
261 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
262 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) || \
263 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
264 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
265 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay)) && \
266 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
267#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
268#define STM32_PLL_SRC_MSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
269#define STM32_PLL_SRC_MSIS DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
270#define STM32_PLL_SRC_HSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
271#define STM32_PLL_SRC_HSE DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
272#define STM32_PLL_SRC_PLL2 DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
273#else
274#define STM32_PLL_SRC_MSI CONFIG_CLOCK_STM32_PLL_SRC_MSI
275#define STM32_PLL_SRC_HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI
276#define STM32_PLL_SRC_HSE CONFIG_CLOCK_STM32_PLL_SRC_HSE
277#define STM32_PLL_SRC_PLL2 CONFIG_CLOCK_STM32_PLL_SRC_PLL2
278#endif
279
280#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
281#define STM32_LSE_CLOCK DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
282#else
283#define STM32_LSE_CLOCK CONFIG_CLOCK_STM32_LSE
284#endif
285
286#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
287 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
288#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
289#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
290#define STM32_MSI_RANGE CONFIG_CLOCK_STM32_MSI_RANGE
291#endif
292
293#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
294#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
295#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
296#define STM32_MSI_PLL_MODE CONFIG_CLOCK_STM32_MSI_PLL_MODE
297#endif
298
299#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
300#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
301#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
302#endif
303
304#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay)
305#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
306#else
307#define STM32_HSI_DIVISOR CONFIG_CLOCK_STM32_HSI_DIVISOR
308#endif
309
310#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
311#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
312#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
313#define STM32_HSE_BYPASS CONFIG_CLOCK_STM32_HSE_BYPASS
314#endif
315
316#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
317#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
318#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
319#endif
320
321struct stm32_pclken {
322 uint32_t bus;
323 uint32_t enr;
324};
325
326#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */
clock_control.h
Public Clock Control APIs.
uint32_t
__UINT32_TYPE__ uint32_t
Definition: stdint.h:60
stm32_clock.h
stm32_pclken
Definition: stm32_clock_control.h:321
stm32_pclken::bus
uint32_t bus
Definition: stm32_clock_control.h:322
stm32_pclken::enr
uint32_t enr
Definition: stm32_clock_control.h:323