gpio.h

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/*
 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
 * Copyright (c) 2019 Piotr Mienkowski
 * Copyright (c) 2017 ARM Ltd
 * Copyright (c) 2015-2016 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_H_
#define ZEPHYR_INCLUDE_DRIVERS_GPIO_H_
 
#include <sys/__assert.h>
#include <sys/slist.h>
 
#include <zephyr/types.h>
#include <stddef.h>
#include <device.h>
#include <dt-bindings/gpio/gpio.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define GPIO_INPUT              (1U << 8)
 
#define GPIO_OUTPUT             (1U << 9)
 
#define GPIO_DISCONNECTED       0
 
/* Initializes output to a low state. */
#define GPIO_OUTPUT_INIT_LOW    (1U << 10)
 
/* Initializes output to a high state. */
#define GPIO_OUTPUT_INIT_HIGH   (1U << 11)
 
/* Initializes output based on logic level */
#define GPIO_OUTPUT_INIT_LOGICAL (1U << 12)
 
#define GPIO_OUTPUT_LOW         (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW)
#define GPIO_OUTPUT_HIGH        (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH)
#define GPIO_OUTPUT_INACTIVE    (GPIO_OUTPUT |                  \
                                 GPIO_OUTPUT_INIT_LOW |         \
                                 GPIO_OUTPUT_INIT_LOGICAL)
#define GPIO_OUTPUT_ACTIVE      (GPIO_OUTPUT |                  \
                                 GPIO_OUTPUT_INIT_HIGH |        \
                                 GPIO_OUTPUT_INIT_LOGICAL)
 
#define GPIO_INT_DISABLE               (1U << 13)
 
/* Enables GPIO pin interrupt. */
#define GPIO_INT_ENABLE                (1U << 14)
 
/* GPIO interrupt is sensitive to logical levels.
 *
 * This is a component flag that should be combined with other
 * `GPIO_INT_*` flags to produce a meaningful configuration.
 */
#define GPIO_INT_LEVELS_LOGICAL        (1U << 15)
 
/* GPIO interrupt is edge sensitive.
 *
 * Note: by default interrupts are level sensitive.
 *
 * This is a component flag that should be combined with other
 * `GPIO_INT_*` flags to produce a meaningful configuration.
 */
#define GPIO_INT_EDGE                  (1U << 16)
 
/* Trigger detection when input state is (or transitions to) physical low or
 * logical 0 level.
 *
 * This is a component flag that should be combined with other
 * `GPIO_INT_*` flags to produce a meaningful configuration.
 */
#define GPIO_INT_LOW_0                 (1U << 17)
 
/* Trigger detection on input state is (or transitions to) physical high or
 * logical 1 level.
 *
 * This is a component flag that should be combined with other
 * `GPIO_INT_*` flags to produce a meaningful configuration.
 */
#define GPIO_INT_HIGH_1                (1U << 18)
 
#define GPIO_INT_MASK                  (GPIO_INT_DISABLE | \
                                        GPIO_INT_ENABLE | \
                                        GPIO_INT_LEVELS_LOGICAL | \
                                        GPIO_INT_EDGE | \
                                        GPIO_INT_LOW_0 | \
                                        GPIO_INT_HIGH_1)
 
#define GPIO_INT_EDGE_RISING           (GPIO_INT_ENABLE | \
                                        GPIO_INT_EDGE | \
                                        GPIO_INT_HIGH_1)
 
#define GPIO_INT_EDGE_FALLING          (GPIO_INT_ENABLE | \
                                        GPIO_INT_EDGE | \
                                        GPIO_INT_LOW_0)
 
#define GPIO_INT_EDGE_BOTH             (GPIO_INT_ENABLE | \
                                        GPIO_INT_EDGE | \
                                        GPIO_INT_LOW_0 | \
                                        GPIO_INT_HIGH_1)
 
#define GPIO_INT_LEVEL_LOW             (GPIO_INT_ENABLE | \
                                        GPIO_INT_LOW_0)
 
#define GPIO_INT_LEVEL_HIGH            (GPIO_INT_ENABLE | \
                                        GPIO_INT_HIGH_1)
 
#define GPIO_INT_EDGE_TO_INACTIVE      (GPIO_INT_ENABLE | \
                                        GPIO_INT_LEVELS_LOGICAL | \
                                        GPIO_INT_EDGE | \
                                        GPIO_INT_LOW_0)
 
#define GPIO_INT_EDGE_TO_ACTIVE        (GPIO_INT_ENABLE | \
                                        GPIO_INT_LEVELS_LOGICAL | \
                                        GPIO_INT_EDGE | \
                                        GPIO_INT_HIGH_1)
 
#define GPIO_INT_LEVEL_INACTIVE        (GPIO_INT_ENABLE | \
                                        GPIO_INT_LEVELS_LOGICAL | \
                                        GPIO_INT_LOW_0)
 
#define GPIO_INT_LEVEL_ACTIVE          (GPIO_INT_ENABLE | \
                                        GPIO_INT_LEVELS_LOGICAL | \
                                        GPIO_INT_HIGH_1)
 
#define GPIO_INT_DEBOUNCE              (1U << 19)
 
#define GPIO_DS_LOW_POS 20
#define GPIO_DS_LOW_MASK (0x3U << GPIO_DS_LOW_POS)
#define GPIO_DS_DFLT_LOW (0x0U << GPIO_DS_LOW_POS)
 
#define GPIO_DS_ALT_LOW (0x1U << GPIO_DS_LOW_POS)
 
#define GPIO_DS_HIGH_POS 22
#define GPIO_DS_HIGH_MASK (0x3U << GPIO_DS_HIGH_POS)
#define GPIO_DS_DFLT_HIGH (0x0U << GPIO_DS_HIGH_POS)
 
#define GPIO_DS_ALT_HIGH (0x1U << GPIO_DS_HIGH_POS)
#define GPIO_DIR_MASK           (GPIO_INPUT | GPIO_OUTPUT)
typedef uint32_t gpio_port_pins_t;
 
typedef uint32_t gpio_port_value_t;
 
typedef uint8_t gpio_pin_t;
 
typedef uint8_t gpio_dt_flags_t;
 
typedef uint32_t gpio_flags_t;
 
struct gpio_dt_spec {
        const struct device *port;
        gpio_pin_t pin;
        gpio_dt_flags_t dt_flags;
};
 
#define GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, idx)                            \
        {                                                                      \
                .port = DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(node_id, prop, idx)),\
                .pin = DT_GPIO_PIN_BY_IDX(node_id, prop, idx),                 \
                .dt_flags = DT_GPIO_FLAGS_BY_IDX(node_id, prop, idx),          \
        }
 
#define GPIO_DT_SPEC_GET_BY_IDX_OR(node_id, prop, idx, default_value)   \
        COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop),                    \
                    (GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, idx)),      \
                    (default_value))
 
#define GPIO_DT_SPEC_GET(node_id, prop) \
        GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, 0)
 
#define GPIO_DT_SPEC_GET_OR(node_id, prop, default_value) \
        GPIO_DT_SPEC_GET_BY_IDX_OR(node_id, prop, 0, default_value)
 
#define GPIO_DT_SPEC_INST_GET_BY_IDX(inst, prop, idx) \
        GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst), prop, idx)
 
#define GPIO_DT_SPEC_INST_GET_BY_IDX_OR(inst, prop, idx, default_value) \
        GPIO_DT_SPEC_GET_BY_IDX_OR(DT_DRV_INST(inst), prop, idx, default_value)
 
#define GPIO_DT_SPEC_INST_GET(inst, prop) \
        GPIO_DT_SPEC_INST_GET_BY_IDX(inst, prop, 0)
 
#define GPIO_DT_SPEC_INST_GET_OR(inst, prop, default_value) \
        GPIO_DT_SPEC_INST_GET_BY_IDX_OR(inst, prop, 0, default_value)
 
#define GPIO_MAX_PINS_PER_PORT (sizeof(gpio_port_pins_t) * __CHAR_BIT__)
 
struct gpio_driver_config {
        /* Mask identifying pins supported by the controller.
         *
         * Initialization of this mask is the responsibility of device
         * instance generation in the driver.
         */
        gpio_port_pins_t port_pin_mask;
};
 
struct gpio_driver_data {
        /* Mask identifying pins that are configured as active low.
         *
         * Management of this mask is the responsibility of the
         * wrapper functions in this header.
         */
        gpio_port_pins_t invert;
};
 
struct gpio_callback;
 
typedef void (*gpio_callback_handler_t)(const struct device *port,
                                        struct gpio_callback *cb,
                                        gpio_port_pins_t pins);
 
struct gpio_callback {
        sys_snode_t node;
 
        gpio_callback_handler_t handler;
 
        gpio_port_pins_t pin_mask;
};
 
/* Used by driver api function pin_interrupt_configure, these are defined
 * in terms of the public flags so we can just mask and pass them
 * through to the driver api
 */
enum gpio_int_mode {
        GPIO_INT_MODE_DISABLED = GPIO_INT_DISABLE,
        GPIO_INT_MODE_LEVEL = GPIO_INT_ENABLE,
        GPIO_INT_MODE_EDGE = GPIO_INT_ENABLE | GPIO_INT_EDGE,
};
 
enum gpio_int_trig {
        /* Trigger detection when input state is (or transitions to)
         * physical low. (Edge Failing or Active Low) */
        GPIO_INT_TRIG_LOW = GPIO_INT_LOW_0,
        /* Trigger detection when input state is (or transitions to)
         * physical high. (Edge Rising or Active High) */
        GPIO_INT_TRIG_HIGH = GPIO_INT_HIGH_1,
        /* Trigger detection on pin rising or falling edge. */
        GPIO_INT_TRIG_BOTH = GPIO_INT_LOW_0 | GPIO_INT_HIGH_1,
};
 
__subsystem struct gpio_driver_api {
        int (*pin_configure)(const struct device *port, gpio_pin_t pin,
                             gpio_flags_t flags);
        int (*port_get_raw)(const struct device *port,
                            gpio_port_value_t *value);
        int (*port_set_masked_raw)(const struct device *port,
                                   gpio_port_pins_t mask,
                                   gpio_port_value_t value);
        int (*port_set_bits_raw)(const struct device *port,
                                 gpio_port_pins_t pins);
        int (*port_clear_bits_raw)(const struct device *port,
                                   gpio_port_pins_t pins);
        int (*port_toggle_bits)(const struct device *port,
                                gpio_port_pins_t pins);
        int (*pin_interrupt_configure)(const struct device *port,
                                       gpio_pin_t pin,
                                       enum gpio_int_mode, enum gpio_int_trig);
        int (*manage_callback)(const struct device *port,
                               struct gpio_callback *cb,
                               bool set);
        uint32_t (*get_pending_int)(const struct device *dev);
};
 
__syscall int gpio_pin_interrupt_configure(const struct device *port,
                                           gpio_pin_t pin,
                                           gpio_flags_t flags);
 
static inline int z_impl_gpio_pin_interrupt_configure(const struct device *port,
                                                      gpio_pin_t pin,
                                                      gpio_flags_t flags)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)port->api;
        const struct gpio_driver_config *const cfg =
                (const struct gpio_driver_config *)port->config;
        const struct gpio_driver_data *const data =
                (const struct gpio_driver_data *)port->data;
        enum gpio_int_trig trig;
        enum gpio_int_mode mode;
 
        __ASSERT_NO_MSG((flags & GPIO_INT_DEBOUNCE) == 0);
 
        __ASSERT((flags & (GPIO_INT_DISABLE | GPIO_INT_ENABLE))
                 != (GPIO_INT_DISABLE | GPIO_INT_ENABLE),
                 "Cannot both enable and disable interrupts");
 
        __ASSERT((flags & (GPIO_INT_DISABLE | GPIO_INT_ENABLE)) != 0U,
                 "Must either enable or disable interrupts");
 
        __ASSERT(((flags & GPIO_INT_ENABLE) == 0) ||
                 ((flags & GPIO_INT_EDGE) != 0) ||
                 ((flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1)) !=
                  (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1)),
                 "Only one of GPIO_INT_LOW_0, GPIO_INT_HIGH_1 can be "
                 "enabled for a level interrupt.");
 
        __ASSERT(((flags & GPIO_INT_ENABLE) == 0) ||
                 ((flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1)) != 0),
                 "At least one of GPIO_INT_LOW_0, GPIO_INT_HIGH_1 has to be "
                 "enabled.");
 
        (void)cfg;
        __ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
                 "Unsupported pin");
 
        if (((flags & GPIO_INT_LEVELS_LOGICAL) != 0) &&
            ((data->invert & (gpio_port_pins_t)BIT(pin)) != 0)) {
                /* Invert signal bits */
                flags ^= (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1);
        }
 
        trig = (enum gpio_int_trig)(flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1));
        mode = (enum gpio_int_mode)(flags & (GPIO_INT_EDGE | GPIO_INT_DISABLE | GPIO_INT_ENABLE));
 
        return api->pin_interrupt_configure(port, pin, mode, trig);
}
 
static inline int gpio_pin_interrupt_configure_dt(const struct gpio_dt_spec *spec,
                                                  gpio_flags_t flags)
{
        return gpio_pin_interrupt_configure(spec->port, spec->pin, flags);
}
 
__syscall int gpio_pin_configure(const struct device *port,
                                 gpio_pin_t pin,
                                 gpio_flags_t flags);
 
static inline int z_impl_gpio_pin_configure(const struct device *port,
                                            gpio_pin_t pin,
                                            gpio_flags_t flags)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)port->api;
        const struct gpio_driver_config *const cfg =
                (const struct gpio_driver_config *)port->config;
        struct gpio_driver_data *data =
                (struct gpio_driver_data *)port->data;
 
        __ASSERT((flags & GPIO_INT_MASK) == 0,
                 "Interrupt flags are not supported");
 
        __ASSERT((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) !=
                 (GPIO_PULL_UP | GPIO_PULL_DOWN),
                 "Pull Up and Pull Down should not be enabled simultaneously");
 
        __ASSERT((flags & GPIO_OUTPUT) != 0 || (flags & GPIO_SINGLE_ENDED) == 0,
                 "Output needs to be enabled for 'Open Drain', 'Open Source' "
                 "mode to be supported");
 
        __ASSERT_NO_MSG((flags & GPIO_SINGLE_ENDED) != 0 ||
                        (flags & GPIO_LINE_OPEN_DRAIN) == 0);
 
        __ASSERT((flags & (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH)) == 0
                 || (flags & GPIO_OUTPUT) != 0,
                 "Output needs to be enabled to be initialized low or high");
 
        __ASSERT((flags & (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH))
                 != (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH),
                 "Output cannot be initialized low and high");
 
        if (((flags & GPIO_OUTPUT_INIT_LOGICAL) != 0)
            && ((flags & (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH)) != 0)
            && ((flags & GPIO_ACTIVE_LOW) != 0)) {
                flags ^= GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH;
        }
 
        flags &= ~GPIO_OUTPUT_INIT_LOGICAL;
 
        (void)cfg;
        __ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
                 "Unsupported pin");
 
        if ((flags & GPIO_ACTIVE_LOW) != 0) {
                data->invert |= (gpio_port_pins_t)BIT(pin);
        } else {
                data->invert &= ~(gpio_port_pins_t)BIT(pin);
        }
 
        return api->pin_configure(port, pin, flags);
}
 
static inline int gpio_pin_configure_dt(const struct gpio_dt_spec *spec,
                                        gpio_flags_t extra_flags)
{
        return gpio_pin_configure(spec->port,
                                  spec->pin,
                                  spec->dt_flags | extra_flags);
}
 
__syscall int gpio_port_get_raw(const struct device *port,
                                gpio_port_value_t *value);
 
static inline int z_impl_gpio_port_get_raw(const struct device *port,
                                           gpio_port_value_t *value)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)port->api;
 
        return api->port_get_raw(port, value);
}
 
static inline int gpio_port_get(const struct device *port,
                                gpio_port_value_t *value)
{
        const struct gpio_driver_data *const data =
                        (const struct gpio_driver_data *)port->data;
        int ret;
 
        ret = gpio_port_get_raw(port, value);
        if (ret == 0) {
                *value ^= data->invert;
        }
 
        return ret;
}
 
__syscall int gpio_port_set_masked_raw(const struct device *port,
                                       gpio_port_pins_t mask,
                                       gpio_port_value_t value);
 
static inline int z_impl_gpio_port_set_masked_raw(const struct device *port,
                                                  gpio_port_pins_t mask,
                                                  gpio_port_value_t value)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)port->api;
 
        return api->port_set_masked_raw(port, mask, value);
}
 
static inline int gpio_port_set_masked(const struct device *port,
                                       gpio_port_pins_t mask,
                                       gpio_port_value_t value)
{
        const struct gpio_driver_data *const data =
                        (const struct gpio_driver_data *)port->data;
 
        value ^= data->invert;
 
        return gpio_port_set_masked_raw(port, mask, value);
}
 
__syscall int gpio_port_set_bits_raw(const struct device *port,
                                     gpio_port_pins_t pins);
 
static inline int z_impl_gpio_port_set_bits_raw(const struct device *port,
                                                gpio_port_pins_t pins)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)port->api;
 
        return api->port_set_bits_raw(port, pins);
}
 
static inline int gpio_port_set_bits(const struct device *port,
                                     gpio_port_pins_t pins)
{
        return gpio_port_set_masked(port, pins, pins);
}
 
__syscall int gpio_port_clear_bits_raw(const struct device *port,
                                       gpio_port_pins_t pins);
 
static inline int z_impl_gpio_port_clear_bits_raw(const struct device *port,
                                                  gpio_port_pins_t pins)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)port->api;
 
        return api->port_clear_bits_raw(port, pins);
}
 
static inline int gpio_port_clear_bits(const struct device *port,
                                       gpio_port_pins_t pins)
{
        return gpio_port_set_masked(port, pins, 0);
}
 
__syscall int gpio_port_toggle_bits(const struct device *port,
                                    gpio_port_pins_t pins);
 
static inline int z_impl_gpio_port_toggle_bits(const struct device *port,
                                               gpio_port_pins_t pins)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)port->api;
 
        return api->port_toggle_bits(port, pins);
}
 
static inline int gpio_port_set_clr_bits_raw(const struct device *port,
                                             gpio_port_pins_t set_pins,
                                             gpio_port_pins_t clear_pins)
{
        __ASSERT((set_pins & clear_pins) == 0, "Set and Clear pins overlap");
 
        return gpio_port_set_masked_raw(port, set_pins | clear_pins, set_pins);
}
 
static inline int gpio_port_set_clr_bits(const struct device *port,
                                         gpio_port_pins_t set_pins,
                                         gpio_port_pins_t clear_pins)
{
        __ASSERT((set_pins & clear_pins) == 0, "Set and Clear pins overlap");
 
        return gpio_port_set_masked(port, set_pins | clear_pins, set_pins);
}
 
static inline int gpio_pin_get_raw(const struct device *port, gpio_pin_t pin)
{
        const struct gpio_driver_config *const cfg =
                (const struct gpio_driver_config *)port->config;
        gpio_port_value_t value;
        int ret;
 
        (void)cfg;
        __ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
                 "Unsupported pin");
 
        ret = gpio_port_get_raw(port, &value);
        if (ret == 0) {
                ret = (value & (gpio_port_pins_t)BIT(pin)) != 0 ? 1 : 0;
        }
 
        return ret;
}
 
static inline int gpio_pin_get(const struct device *port, gpio_pin_t pin)
{
        const struct gpio_driver_config *const cfg =
                (const struct gpio_driver_config *)port->config;
        gpio_port_value_t value;
        int ret;
 
        (void)cfg;
        __ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
                 "Unsupported pin");
 
        ret = gpio_port_get(port, &value);
        if (ret == 0) {
                ret = (value & (gpio_port_pins_t)BIT(pin)) != 0 ? 1 : 0;
        }
 
        return ret;
}
 
static inline int gpio_pin_get_dt(const struct gpio_dt_spec *spec)
{
        return gpio_pin_get(spec->port, spec->pin);
}
 
static inline int gpio_pin_set_raw(const struct device *port, gpio_pin_t pin,
                                   int value)
{
        const struct gpio_driver_config *const cfg =
                (const struct gpio_driver_config *)port->config;
        int ret;
 
        (void)cfg;
        __ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
                 "Unsupported pin");
 
        if (value != 0) {
                ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
        } else {
                ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
        }
 
        return ret;
}
 
static inline int gpio_pin_set(const struct device *port, gpio_pin_t pin,
                               int value)
{
        const struct gpio_driver_config *const cfg =
                (const struct gpio_driver_config *)port->config;
        const struct gpio_driver_data *const data =
                        (const struct gpio_driver_data *)port->data;
 
        (void)cfg;
        __ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
                 "Unsupported pin");
 
        if (data->invert & (gpio_port_pins_t)BIT(pin)) {
                value = (value != 0) ? 0 : 1;
        }
 
        return gpio_pin_set_raw(port, pin, value);
}
 
static inline int gpio_pin_set_dt(const struct gpio_dt_spec *spec, int value)
{
        return gpio_pin_set(spec->port, spec->pin, value);
}
 
static inline int gpio_pin_toggle(const struct device *port, gpio_pin_t pin)
{
        const struct gpio_driver_config *const cfg =
                (const struct gpio_driver_config *)port->config;
 
        (void)cfg;
        __ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
                 "Unsupported pin");
 
        return gpio_port_toggle_bits(port, (gpio_port_pins_t)BIT(pin));
}
 
static inline int gpio_pin_toggle_dt(const struct gpio_dt_spec *spec)
{
        return gpio_pin_toggle(spec->port, spec->pin);
}
 
static inline void gpio_init_callback(struct gpio_callback *callback,
                                      gpio_callback_handler_t handler,
                                      gpio_port_pins_t pin_mask)
{
        __ASSERT(callback, "Callback pointer should not be NULL");
        __ASSERT(handler, "Callback handler pointer should not be NULL");
 
        callback->handler = handler;
        callback->pin_mask = pin_mask;
}
 
static inline int gpio_add_callback(const struct device *port,
                                    struct gpio_callback *callback)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)port->api;
 
        if (api->manage_callback == NULL) {
                return -ENOTSUP;
        }
 
        return api->manage_callback(port, callback, true);
}
 
static inline int gpio_remove_callback(const struct device *port,
                                       struct gpio_callback *callback)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)port->api;
 
        if (api->manage_callback == NULL) {
                return -ENOTSUP;
        }
 
        return api->manage_callback(port, callback, false);
}
 
__syscall int gpio_get_pending_int(const struct device *dev);
 
static inline int z_impl_gpio_get_pending_int(const struct device *dev)
{
        const struct gpio_driver_api *api =
                (const struct gpio_driver_api *)dev->api;
 
        if (api->get_pending_int == NULL) {
                return -ENOTSUP;
        }
 
        return api->get_pending_int(dev);
}
 
#ifdef __cplusplus
}
#endif
 
#include <syscalls/gpio.h>
 
#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_H_ */