Zephyr API Documentation
2.7.0-rc2
A Scalable Open Source RTOS
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CMSIS interface file. More...
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Macros | |
#define | CPACR_CP10_Pos 20U |
#define | CPACR_CP10_Msk (3UL << CPACR_CP10_Pos) |
#define | CPACR_CP10_NO_ACCESS (0UL << CPACR_CP10_Pos) |
#define | CPACR_CP10_PRIV_ACCESS (1UL << CPACR_CP10_Pos) |
#define | CPACR_CP10_RESERVED (2UL << CPACR_CP10_Pos) |
#define | CPACR_CP10_FULL_ACCESS (3UL << CPACR_CP10_Pos) |
#define | CPACR_CP11_Pos 22U |
#define | CPACR_CP11_Msk (3UL << CPACR_CP11_Pos) |
#define | CPACR_CP11_NO_ACCESS (0UL << CPACR_CP11_Pos) |
#define | CPACR_CP11_PRIV_ACCESS (1UL << CPACR_CP11_Pos) |
#define | CPACR_CP11_RESERVED (2UL << CPACR_CP11_Pos) |
#define | CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos) |
#define | SCB_UFSR (*((__IOM uint16_t *) &SCB->CFSR + 1)) |
#define | SCB_BFSR (*((__IOM uint8_t *) &SCB->CFSR + 1)) |
#define | SCB_MMFSR (*((__IOM uint8_t *) &SCB->CFSR)) |
Enumerations | |
enum | IRQn_Type { Reset_IRQn = -15 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 } |
CMSIS interface file.
This header contains the interface to the ARM CMSIS Core headers.
#define CPACR_CP10_FULL_ACCESS (3UL << CPACR_CP10_Pos) |
#define CPACR_CP10_Msk (3UL << CPACR_CP10_Pos) |
#define CPACR_CP10_NO_ACCESS (0UL << CPACR_CP10_Pos) |
#define CPACR_CP10_Pos 20U |
#define CPACR_CP10_PRIV_ACCESS (1UL << CPACR_CP10_Pos) |
#define CPACR_CP10_RESERVED (2UL << CPACR_CP10_Pos) |
#define CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos) |
#define CPACR_CP11_Msk (3UL << CPACR_CP11_Pos) |
#define CPACR_CP11_NO_ACCESS (0UL << CPACR_CP11_Pos) |
#define CPACR_CP11_Pos 22U |
#define CPACR_CP11_PRIV_ACCESS (1UL << CPACR_CP11_Pos) |
#define CPACR_CP11_RESERVED (2UL << CPACR_CP11_Pos) |
#define SCB_BFSR (*((__IOM uint8_t *) &SCB->CFSR + 1)) |
#define SCB_MMFSR (*((__IOM uint8_t *) &SCB->CFSR)) |
#define SCB_UFSR (*((__IOM uint16_t *) &SCB->CFSR + 1)) |
enum IRQn_Type |