Data Structures
struct	arm_mmu_region

struct	arm_mmu_config

struct	arm_mmu_ptables

Macros
#define	MT_TYPE_MASK 0x7U

#define	MT_TYPE(attr) (attr & MT_TYPE_MASK)

#define	MT_DEVICE_nGnRnE 0U

#define	MT_DEVICE_nGnRE 1U

#define	MT_DEVICE_GRE 2U

#define	MT_NORMAL_NC 3U

#define	MT_NORMAL 4U

#define	MT_NORMAL_WT 5U

#define	MEMORY_ATTRIBUTES

#define	MT_PERM_SHIFT 3U

#define	MT_SEC_SHIFT 4U

#define	MT_P_EXECUTE_SHIFT 5U

#define	MT_U_EXECUTE_SHIFT 6U

#define	MT_RW_AP_SHIFT 7U

#define	MT_NO_OVERWRITE_SHIFT 8U

#define	MT_RO (0U << MT_PERM_SHIFT)

#define	MT_RW (1U << MT_PERM_SHIFT)

#define	MT_RW_AP_ELx (1U << MT_RW_AP_SHIFT)

#define	MT_RW_AP_EL_HIGHER (0U << MT_RW_AP_SHIFT)

#define	MT_SECURE (0U << MT_SEC_SHIFT)

#define	MT_NS (1U << MT_SEC_SHIFT)

#define	MT_P_EXECUTE (0U << MT_P_EXECUTE_SHIFT)

#define	MT_P_EXECUTE_NEVER (1U << MT_P_EXECUTE_SHIFT)

#define	MT_U_EXECUTE (0U << MT_U_EXECUTE_SHIFT)

#define	MT_U_EXECUTE_NEVER (1U << MT_U_EXECUTE_SHIFT)

#define	MT_NO_OVERWRITE (1U << MT_NO_OVERWRITE_SHIFT)

#define	MT_P_RW_U_RW (MT_RW \| MT_RW_AP_ELx \| MT_P_EXECUTE_NEVER \| MT_U_EXECUTE_NEVER)

#define	MT_P_RW_U_NA (MT_RW \| MT_RW_AP_EL_HIGHER \| MT_P_EXECUTE_NEVER \| MT_U_EXECUTE_NEVER)

#define	MT_P_RO_U_RO (MT_RO \| MT_RW_AP_ELx \| MT_P_EXECUTE_NEVER \| MT_U_EXECUTE_NEVER)

#define	MT_P_RO_U_NA (MT_RO \| MT_RW_AP_EL_HIGHER \| MT_P_EXECUTE_NEVER \| MT_U_EXECUTE_NEVER)

#define	MT_P_RO_U_RX (MT_RO \| MT_RW_AP_ELx \| MT_P_EXECUTE_NEVER \| MT_U_EXECUTE)

#define	MT_P_RX_U_RX (MT_RO \| MT_RW_AP_ELx \| MT_P_EXECUTE \| MT_U_EXECUTE)

#define	MT_P_RX_U_NA (MT_RO \| MT_RW_AP_EL_HIGHER \| MT_P_EXECUTE \| MT_U_EXECUTE_NEVER)

#define	MT_DEFAULT_SECURE_STATE MT_SECURE

#define	PTE_DESC_TYPE_MASK 3U

#define	PTE_BLOCK_DESC 1U

#define	PTE_TABLE_DESC 3U

#define	PTE_PAGE_DESC 3U

#define	PTE_INVALID_DESC 0U

#define	PTE_BLOCK_DESC_MEMTYPE(x) (x << 2)

#define	PTE_BLOCK_DESC_NS (1ULL << 5)

#define	PTE_BLOCK_DESC_AP_ELx (1ULL << 6)

#define	PTE_BLOCK_DESC_AP_EL_HIGHER (0ULL << 6)

#define	PTE_BLOCK_DESC_AP_RO (1ULL << 7)

#define	PTE_BLOCK_DESC_AP_RW (0ULL << 7)

#define	PTE_BLOCK_DESC_NON_SHARE (0ULL << 8)

#define	PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8)

#define	PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8)

#define	PTE_BLOCK_DESC_AF (1ULL << 10)

#define	PTE_BLOCK_DESC_NG (1ULL << 11)

#define	PTE_BLOCK_DESC_PXN (1ULL << 53)

#define	PTE_BLOCK_DESC_UXN (1ULL << 54)

#define	TCR_EL1_IPS_SHIFT 32U

#define	TCR_EL2_PS_SHIFT 16U

#define	TCR_EL3_PS_SHIFT 16U

#define	TCR_T0SZ_SHIFT 0U

#define	TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT)

#define	TCR_IRGN_NC (0ULL << 8)

#define	TCR_IRGN_WBWA (1ULL << 8)

#define	TCR_IRGN_WT (2ULL << 8)

#define	TCR_IRGN_WBNWA (3ULL << 8)

#define	TCR_IRGN_MASK (3ULL << 8)

#define	TCR_ORGN_NC (0ULL << 10)

#define	TCR_ORGN_WBWA (1ULL << 10)

#define	TCR_ORGN_WT (2ULL << 10)

#define	TCR_ORGN_WBNWA (3ULL << 10)

#define	TCR_ORGN_MASK (3ULL << 10)

#define	TCR_SHARED_NON (0ULL << 12)

#define	TCR_SHARED_OUTER (2ULL << 12)

#define	TCR_SHARED_INNER (3ULL << 12)

#define	TCR_TG0_4K (0ULL << 14)

#define	TCR_TG0_64K (1ULL << 14)

#define	TCR_TG0_16K (2ULL << 14)

#define	TCR_EPD1_DISABLE (1ULL << 23)

#define	TCR_PS_BITS_4GB 0x0ULL

#define	TCR_PS_BITS_64GB 0x1ULL

#define	TCR_PS_BITS_1TB 0x2ULL

#define	TCR_PS_BITS_4TB 0x3ULL

#define	TCR_PS_BITS_16TB 0x4ULL

#define	TCR_PS_BITS_256TB 0x5ULL

#define	MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs)

#define	MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) MMU_REGION_ENTRY(name, adr, adr, sz, attrs)

Variables
const struct arm_mmu_config	mmu_config

Macro Definition Documentation

◆ MEMORY_ATTRIBUTES

#define MEMORY_ATTRIBUTES

Value:

                                ((0x00 << (MT_DEVICE_nGnRnE * 8)) |     \
                                (0x04 << (MT_DEVICE_nGnRE * 8))   |     \
                                (0x0c << (MT_DEVICE_GRE * 8))     |     \
                                (0x44 << (MT_NORMAL_NC * 8))      |     \
                                (0xffUL << (MT_NORMAL * 8))       |     \
                                (0xbbUL << (MT_NORMAL_WT * 8)))

◆ MMU_REGION_ENTRY

#define MMU_REGION_ENTRY	(	_name,
		_base_pa,
		_base_va,
		_size,
		_attrs
	)

Value:

        {\
                .name = _name, \
                .base_pa = _base_pa, \
                .base_va = _base_va, \
                .size = _size, \
                .attrs = _attrs, \
        }

◆ MMU_REGION_FLAT_ENTRY

#define MMU_REGION_FLAT_ENTRY	(	name,
		adr,
		sz,
		attrs
	)	MMU_REGION_ENTRY(name, adr, adr, sz, attrs)

◆ MT_DEFAULT_SECURE_STATE

#define MT_DEFAULT_SECURE_STATE MT_SECURE

◆ MT_DEVICE_GRE

#define MT_DEVICE_GRE 2U

◆ MT_DEVICE_nGnRE

#define MT_DEVICE_nGnRE 1U

◆ MT_DEVICE_nGnRnE

#define MT_DEVICE_nGnRnE 0U

◆ MT_NO_OVERWRITE

#define MT_NO_OVERWRITE (1U << MT_NO_OVERWRITE_SHIFT)

◆ MT_NO_OVERWRITE_SHIFT

#define MT_NO_OVERWRITE_SHIFT 8U

◆ MT_NORMAL

#define MT_NORMAL 4U

◆ MT_NORMAL_NC

#define MT_NORMAL_NC 3U

◆ MT_NORMAL_WT

#define MT_NORMAL_WT 5U

◆ MT_NS

#define MT_NS (1U << MT_SEC_SHIFT)

◆ MT_P_EXECUTE

#define MT_P_EXECUTE (0U << MT_P_EXECUTE_SHIFT)

◆ MT_P_EXECUTE_NEVER

#define MT_P_EXECUTE_NEVER (1U << MT_P_EXECUTE_SHIFT)

◆ MT_P_EXECUTE_SHIFT

#define MT_P_EXECUTE_SHIFT 5U

◆ MT_P_RO_U_NA

#define MT_P_RO_U_NA (MT_RO | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)

◆ MT_P_RO_U_RO

#define MT_P_RO_U_RO (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)

◆ MT_P_RO_U_RX

#define MT_P_RO_U_RX (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE)

◆ MT_P_RW_U_NA

#define MT_P_RW_U_NA (MT_RW | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)

◆ MT_P_RW_U_RW

#define MT_P_RW_U_RW (MT_RW | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)

◆ MT_P_RX_U_NA

#define MT_P_RX_U_NA (MT_RO | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE | MT_U_EXECUTE_NEVER)

◆ MT_P_RX_U_RX

#define MT_P_RX_U_RX (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE | MT_U_EXECUTE)

◆ MT_PERM_SHIFT

#define MT_PERM_SHIFT 3U

◆ MT_RO

#define MT_RO (0U << MT_PERM_SHIFT)

◆ MT_RW

#define MT_RW (1U << MT_PERM_SHIFT)

◆ MT_RW_AP_EL_HIGHER

#define MT_RW_AP_EL_HIGHER (0U << MT_RW_AP_SHIFT)

◆ MT_RW_AP_ELx

#define MT_RW_AP_ELx (1U << MT_RW_AP_SHIFT)

◆ MT_RW_AP_SHIFT

#define MT_RW_AP_SHIFT 7U

◆ MT_SEC_SHIFT

#define MT_SEC_SHIFT 4U

◆ MT_SECURE

#define MT_SECURE (0U << MT_SEC_SHIFT)

◆ MT_TYPE

#define MT_TYPE ( attr ) (attr & MT_TYPE_MASK)

◆ MT_TYPE_MASK

#define MT_TYPE_MASK 0x7U

◆ MT_U_EXECUTE

#define MT_U_EXECUTE (0U << MT_U_EXECUTE_SHIFT)

◆ MT_U_EXECUTE_NEVER

#define MT_U_EXECUTE_NEVER (1U << MT_U_EXECUTE_SHIFT)

◆ MT_U_EXECUTE_SHIFT

#define MT_U_EXECUTE_SHIFT 6U

◆ PTE_BLOCK_DESC

#define PTE_BLOCK_DESC 1U

◆ PTE_BLOCK_DESC_AF

#define PTE_BLOCK_DESC_AF (1ULL << 10)

◆ PTE_BLOCK_DESC_AP_EL_HIGHER

#define PTE_BLOCK_DESC_AP_EL_HIGHER (0ULL << 6)

◆ PTE_BLOCK_DESC_AP_ELx

#define PTE_BLOCK_DESC_AP_ELx (1ULL << 6)

◆ PTE_BLOCK_DESC_AP_RO

#define PTE_BLOCK_DESC_AP_RO (1ULL << 7)

◆ PTE_BLOCK_DESC_AP_RW

#define PTE_BLOCK_DESC_AP_RW (0ULL << 7)

◆ PTE_BLOCK_DESC_INNER_SHARE

#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8)

◆ PTE_BLOCK_DESC_MEMTYPE

#define PTE_BLOCK_DESC_MEMTYPE ( x ) (x << 2)

◆ PTE_BLOCK_DESC_NG

#define PTE_BLOCK_DESC_NG (1ULL << 11)

◆ PTE_BLOCK_DESC_NON_SHARE

#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8)

◆ PTE_BLOCK_DESC_NS

#define PTE_BLOCK_DESC_NS (1ULL << 5)

◆ PTE_BLOCK_DESC_OUTER_SHARE

#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8)

◆ PTE_BLOCK_DESC_PXN

#define PTE_BLOCK_DESC_PXN (1ULL << 53)

◆ PTE_BLOCK_DESC_UXN

#define PTE_BLOCK_DESC_UXN (1ULL << 54)

◆ PTE_DESC_TYPE_MASK

#define PTE_DESC_TYPE_MASK 3U

◆ PTE_INVALID_DESC

#define PTE_INVALID_DESC 0U

◆ PTE_PAGE_DESC

#define PTE_PAGE_DESC 3U

◆ PTE_TABLE_DESC

#define PTE_TABLE_DESC 3U

◆ TCR_EL1_IPS_SHIFT

#define TCR_EL1_IPS_SHIFT 32U

◆ TCR_EL2_PS_SHIFT

#define TCR_EL2_PS_SHIFT 16U

◆ TCR_EL3_PS_SHIFT

#define TCR_EL3_PS_SHIFT 16U

◆ TCR_EPD1_DISABLE

#define TCR_EPD1_DISABLE (1ULL << 23)

◆ TCR_IRGN_MASK

#define TCR_IRGN_MASK (3ULL << 8)

◆ TCR_IRGN_NC

#define TCR_IRGN_NC (0ULL << 8)

◆ TCR_IRGN_WBNWA

#define TCR_IRGN_WBNWA (3ULL << 8)

◆ TCR_IRGN_WBWA

#define TCR_IRGN_WBWA (1ULL << 8)

◆ TCR_IRGN_WT

#define TCR_IRGN_WT (2ULL << 8)

◆ TCR_ORGN_MASK

#define TCR_ORGN_MASK (3ULL << 10)

◆ TCR_ORGN_NC

#define TCR_ORGN_NC (0ULL << 10)

◆ TCR_ORGN_WBNWA

#define TCR_ORGN_WBNWA (3ULL << 10)

◆ TCR_ORGN_WBWA

#define TCR_ORGN_WBWA (1ULL << 10)

◆ TCR_ORGN_WT

#define TCR_ORGN_WT (2ULL << 10)

◆ TCR_PS_BITS_16TB

#define TCR_PS_BITS_16TB 0x4ULL

◆ TCR_PS_BITS_1TB

#define TCR_PS_BITS_1TB 0x2ULL

◆ TCR_PS_BITS_256TB

#define TCR_PS_BITS_256TB 0x5ULL

◆ TCR_PS_BITS_4GB

#define TCR_PS_BITS_4GB 0x0ULL

◆ TCR_PS_BITS_4TB

#define TCR_PS_BITS_4TB 0x3ULL

◆ TCR_PS_BITS_64GB

#define TCR_PS_BITS_64GB 0x1ULL

◆ TCR_SHARED_INNER

#define TCR_SHARED_INNER (3ULL << 12)

◆ TCR_SHARED_NON

#define TCR_SHARED_NON (0ULL << 12)

◆ TCR_SHARED_OUTER

#define TCR_SHARED_OUTER (2ULL << 12)

◆ TCR_T0SZ

#define TCR_T0SZ ( x ) ((64 - (x)) << TCR_T0SZ_SHIFT)

◆ TCR_T0SZ_SHIFT

#define TCR_T0SZ_SHIFT 0U

◆ TCR_TG0_16K

#define TCR_TG0_16K (2ULL << 14)

◆ TCR_TG0_4K

#define TCR_TG0_4K (0ULL << 14)

◆ TCR_TG0_64K

#define TCR_TG0_64K (1ULL << 14)

Variable Documentation

◆ mmu_config

const struct arm_mmu_config mmu_config

extern

Data Structures

Macros

Variables