Zephyr API Documentation  2.7.0-rc2
A Scalable Open Source RTOS
stm32f1-pinctrl.h
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1/*
2 * Copyright (c) 2017 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_STM32_PINCTRLF1_H_
8#define ZEPHYR_STM32_PINCTRLF1_H_
9
10#include <dt-bindings/pinctrl/stm32-pinctrl-common.h>
11
12/* Adapted from Linux: include/dt-bindings/pinctrl/stm32-pinfunc.h */
13
19#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
20#define STM32F1_PINMUX(port, line, mode, remap) \
21 (((PIN_NO(port, line)) << 8) | (mode << 6) | (remap))
22
27#define ALTERNATE 0x0 /* Alternate function output */
28#define GPIO_IN 0x1 /* Input */
29#define ANALOG 0x2 /* Analog */
30
35#define NO_REMAP 0x0 /* No remapping */
36#define REMAP_1 0x1 /* Partial remapping 1 */
37#define REMAP_2 0x2 /* Partial remapping 2 */
38#define REMAP_3 0x3 /* Partial remapping 3 */
39#define REMAP_FULL 0x4 /* Full remapping */
40
56/* Alternate functions */
57/* STM32F1 Pinmux doesn't use explicit alternate functions */
58/* These are kept for compatibility with other STM32 pinmux */
59#define STM32_AFR_MASK 0
60#define STM32_AFR_SHIFT 0
61
62/* Port Mode */
63#define STM32_MODE_INPUT (0x0<<STM32_MODE_INOUT_SHIFT)
64#define STM32_MODE_OUTPUT (0x1<<STM32_MODE_INOUT_SHIFT)
65#define STM32_MODE_INOUT_MASK 0x1
66#define STM32_MODE_INOUT_SHIFT 0
67
68/* Input Port configuration */
69#define STM32_CNF_IN_ANALOG (0x0<<STM32_CNF_IN_SHIFT)
70#define STM32_CNF_IN_FLOAT (0x1<<STM32_CNF_IN_SHIFT)
71#define STM32_CNF_IN_PUPD (0x2<<STM32_CNF_IN_SHIFT)
72#define STM32_CNF_IN_MASK 0x3
73#define STM32_CNF_IN_SHIFT 1
74
75/* Output Port configuration */
76#define STM32_MODE_OUTPUT_MAX_10 (0x0<<STM32_MODE_OSPEED_SHIFT)
77#define STM32_MODE_OUTPUT_MAX_2 (0x1<<STM32_MODE_OSPEED_SHIFT)
78#define STM32_MODE_OUTPUT_MAX_50 (0x2<<STM32_MODE_OSPEED_SHIFT)
79#define STM32_MODE_OSPEED_MASK 0x3
80#define STM32_MODE_OSPEED_SHIFT 3
81
82#define STM32_CNF_PUSH_PULL (0x0<<STM32_CNF_OUT_0_SHIFT)
83#define STM32_CNF_OPEN_DRAIN (0x1<<STM32_CNF_OUT_0_SHIFT)
84#define STM32_CNF_OUT_0_MASK 0x1
85#define STM32_CNF_OUT_0_SHIFT 5
86
87#define STM32_CNF_GP_OUTPUT (0x0<<STM32_CNF_OUT_1_SHIFT)
88#define STM32_CNF_ALT_FUNC (0x1<<STM32_CNF_OUT_1_SHIFT)
89#define STM32_CNF_OUT_1_MASK 0x1
90#define STM32_CNF_OUT_1_SHIFT 6
91
92/* GPIO High impedance/Pull-up/Pull-down */
93#define STM32_PUPD_NO_PULL (0x0<<STM32_PUPD_SHIFT)
94#define STM32_PUPD_PULL_UP (0x1<<STM32_PUPD_SHIFT)
95#define STM32_PUPD_PULL_DOWN (0x2<<STM32_PUPD_SHIFT)
96#define STM32_PUPD_MASK 0x3
97#define STM32_PUPD_SHIFT 7
98
99/* Alternate defines */
100/* IO pin functions are mostly common across STM32 devices. Notable
101 * exception is STM32F1 as these MCUs do not have registers for
102 * configuration of pin's alternate function. The configuration is
103 * done implicitly by setting specific mode and config in MODE and CNF
104 * registers for particular pin.
105 */
106#define STM32_ALTERNATE (STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC)
107
108#define STM32_PIN_USART_TX (STM32_ALTERNATE | STM32_CNF_PUSH_PULL)
109#define STM32_PIN_USART_RX (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
110#define STM32_PIN_I2C (STM32_ALTERNATE | STM32_CNF_OPEN_DRAIN)
111#define STM32_PIN_PWM (STM32_ALTERNATE | STM32_CNF_PUSH_PULL)
112#define STM32_PIN_SPI_MASTER_SCK (STM32_ALTERNATE | STM32_CNF_PUSH_PULL)
113#define STM32_PIN_SPI_SLAVE_SCK (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
114#define STM32_PIN_SPI_MASTER_MOSI (STM32_ALTERNATE | STM32_CNF_PUSH_PULL)
115#define STM32_PIN_SPI_SLAVE_MOSI (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
116#define STM32_PIN_SPI_MASTER_MISO (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
117#define STM32_PIN_SPI_SLAVE_MISO (STM32_ALTERNATE | STM32_CNF_PUSH_PULL)
118#define STM32_PIN_CAN_TX (STM32_ALTERNATE | STM32_CNF_PUSH_PULL)
119#define STM32_PIN_CAN_RX (STM32_MODE_INPUT | STM32_PUPD_PULL_UP)
120
121/*
122 * Reference manual (RM0008)
123 * Section 25.3.1: Slave select (NSS) pin management
124 *
125 * Hardware NSS management:
126 * - NSS output disabled: allows multimaster capability for devices operating
127 * in master mode.
128 * - NSS output enabled: used only when the device operates in master mode.
129 *
130 * Software NSS management:
131 * - External NSS pin remains free for other application uses.
132 *
133 */
134
135/* Hardware master NSS output disabled */
136#define STM32_PIN_SPI_MASTER_NSS (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
137/* Hardware master NSS output enabled */
138#define STM32_PIN_SPI_MASTER_NSS_OE (STM32_MODE_OUTPUT | \
139 STM32_CNF_ALT_FUNC | \
140 STM32_CNF_PUSH_PULL)
141#define STM32_PIN_SPI_SLAVE_NSS (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT)
142#define STM32_PIN_USB (STM32_MODE_INPUT | STM32_CNF_IN_PUPD)
143
144#endif /* ZEPHYR_STM32_PINCTRLF1_H_ */