Zephyr API Documentation  2.7.0-rc2
A Scalable Open Source RTOS
arch.h
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1/*
2 * Copyright (c) 2010-2014 Wind River Systems, Inc.
3 * Copyright (c) 2017 Oticon A/S
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
17#ifndef ZEPHYR_INCLUDE_ARCH_POSIX_ARCH_H_
18#define ZEPHYR_INCLUDE_ARCH_POSIX_ARCH_H_
19
20/* Add include for DTS generated information */
21#include <devicetree.h>
22
23#include <toolchain.h>
24#include <irq.h>
26#include <arch/posix/thread.h>
27#include <board_irq.h> /* Each board must define this */
28#include <sw_isr_table.h>
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
35#ifdef CONFIG_64BIT
36#define ARCH_STACK_PTR_ALIGN 8
37#else
38#define ARCH_STACK_PTR_ALIGN 4
39#endif
40
41struct __esf {
42 uint32_t dummy; /*maybe we will want to add something someday*/
43};
44
45typedef struct __esf z_arch_esf_t;
46
48
49static inline uint32_t arch_k_cycle_get_32(void)
50{
52}
53
54static ALWAYS_INLINE void arch_nop(void)
55{
56 __asm__ volatile("nop");
57}
58
59static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
60{
61 return key == false;
62}
63
64static ALWAYS_INLINE unsigned int arch_irq_lock(void)
65{
66 return posix_irq_lock();
67}
68
69
70static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
71{
73}
74
75#ifdef __cplusplus
76}
77#endif
78
79#endif /* ZEPHYR_INCLUDE_ARCH_POSIX_ARCH_H_ */
Per-arch thread definition.
#define ALWAYS_INLINE
Definition: common.h:116
Devicetree main header.
uint32_t sys_clock_cycle_get_32(void)
static ALWAYS_INLINE void arch_nop(void)
Definition: arch.h:54
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
Definition: arch.h:64
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
Definition: arch.h:70
static uint32_t arch_k_cycle_get_32(void)
Definition: arch.h:49
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
Definition: arch.h:59
unsigned int posix_irq_lock(void)
void posix_irq_unlock(unsigned int key)
static k_spinlock_key_t key
Definition: spinlock_error_case.c:14
__UINT32_TYPE__ uint32_t
Definition: stdint.h:60
Software-managed ISR table.
Macros to abstract toolchain specific capabilities.