Zephyr API Documentation  2.7.0-rc2
A Scalable Open Source RTOS
cpu.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CPU_H_
8#define ZEPHYR_INCLUDE_ARCH_ARM64_CPU_H_
9
10#include <sys/util.h>
11
12#define DAIFSET_FIQ_BIT BIT(0)
13#define DAIFSET_IRQ_BIT BIT(1)
14#define DAIFSET_ABT_BIT BIT(2)
15#define DAIFSET_DBG_BIT BIT(3)
16
17#define DAIFCLR_FIQ_BIT BIT(0)
18#define DAIFCLR_IRQ_BIT BIT(1)
19#define DAIFCLR_ABT_BIT BIT(2)
20#define DAIFCLR_DBG_BIT BIT(3)
21
22#define DAIF_FIQ_BIT BIT(6)
23#define DAIF_IRQ_BIT BIT(7)
24#define DAIF_ABT_BIT BIT(8)
25#define DAIF_DBG_BIT BIT(9)
26
27#define SPSR_DAIF_SHIFT (6)
28#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
29
30#define SPSR_MODE_EL0T (0x0)
31#define SPSR_MODE_EL1T (0x4)
32#define SPSR_MODE_EL1H (0x5)
33#define SPSR_MODE_EL2T (0x8)
34#define SPSR_MODE_EL2H (0x9)
35#define SPSR_MODE_MASK (0xf)
36
37
38#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
39 BIT(22) | BIT(18) | BIT(16) | \
40 BIT(11) | BIT(5) | BIT(4))
41
42#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
43 BIT(22) | BIT(18) | BIT(16) | \
44 BIT(11) | BIT(5) | BIT(4))
45
46#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
47 BIT(22) | BIT(20) | BIT(11))
48
49#define SCTLR_M_BIT BIT(0)
50#define SCTLR_A_BIT BIT(1)
51#define SCTLR_C_BIT BIT(2)
52#define SCTLR_SA_BIT BIT(3)
53#define SCTLR_I_BIT BIT(12)
54
55#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
56
57#define SCR_NS_BIT BIT(0)
58#define SCR_IRQ_BIT BIT(1)
59#define SCR_FIQ_BIT BIT(2)
60#define SCR_EA_BIT BIT(3)
61#define SCR_SMD_BIT BIT(7)
62#define SCR_HCE_BIT BIT(8)
63#define SCR_RW_BIT BIT(10)
64#define SCR_ST_BIT BIT(11)
65
66#define SCR_RES1 (BIT(4) | BIT(5))
67
68/* MPIDR */
69#define MPIDR_AFFLVL_MASK (0xff)
70
71#define MPIDR_AFF0_SHIFT (0)
72#define MPIDR_AFF1_SHIFT (8)
73#define MPIDR_AFF2_SHIFT (16)
74#define MPIDR_AFF3_SHIFT (32)
75
76#define MPIDR_AFFLVL(mpidr, aff_level) \
77 (((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
78
79#define GET_MPIDR() read_sysreg(mpidr_el1)
80#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 0)
81#define IS_PRIMARY_CORE() (!MPIDR_TO_CORE(GET_MPIDR()))
82
83#define MODE_EL_SHIFT (0x2)
84#define MODE_EL_MASK (0x3)
85
86#define MODE_EL3 (0x3)
87#define MODE_EL2 (0x2)
88#define MODE_EL1 (0x1)
89#define MODE_EL0 (0x0)
90
91#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
92
93#define ESR_EC_SHIFT (26)
94#define ESR_EC_MASK BIT_MASK(6)
95#define ESR_ISS_SHIFT (0)
96#define ESR_ISS_MASK BIT_MASK(25)
97#define ESR_IL_SHIFT (25)
98#define ESR_IL_MASK BIT_MASK(1)
99
100#define GET_ESR_EC(esr) (((esr) >> ESR_EC_SHIFT) & ESR_EC_MASK)
101#define GET_ESR_IL(esr) (((esr) >> ESR_IL_SHIFT) & ESR_IL_MASK)
102#define GET_ESR_ISS(esr) (((esr) >> ESR_ISS_SHIFT) & ESR_ISS_MASK)
103
104#define CNTV_CTL_ENABLE_BIT BIT(0)
105#define CNTV_CTL_IMASK_BIT BIT(1)
106
107#define ID_AA64PFR0_EL0_SHIFT (0)
108#define ID_AA64PFR0_EL1_SHIFT (4)
109#define ID_AA64PFR0_EL2_SHIFT (8)
110#define ID_AA64PFR0_EL3_SHIFT (12)
111#define ID_AA64PFR0_ELX_MASK (0xf)
112#define ID_AA64PFR0_SEL2_SHIFT (36)
113#define ID_AA64PFR0_SEL2_MASK (0xf)
114
115/*
116 * TODO: ACTLR is of class implementation defined. All core implementations
117 * in armv8a have the same implementation so far w.r.t few controls.
118 * When there will be differences we have to create core specific headers.
119 */
120#define ACTLR_EL3_CPUACTLR_BIT BIT(0)
121#define ACTLR_EL3_CPUECTLR_BIT BIT(1)
122#define ACTLR_EL3_L2CTLR_BIT BIT(4)
123#define ACTLR_EL3_L2ECTLR_BIT BIT(5)
124#define ACTLR_EL3_L2ACTLR_BIT BIT(6)
125
126#define CPTR_EZ_BIT BIT(8)
127#define CPTR_TFP_BIT BIT(10)
128#define CPTR_TTA_BIT BIT(20)
129#define CPTR_TCPAC_BIT BIT(31)
130
131#define CPTR_EL2_RES1 BIT(13) | BIT(12) | BIT(9) | (0xff)
132
133#define HCR_FMO_BIT BIT(3)
134#define HCR_IMO_BIT BIT(4)
135#define HCR_AMO_BIT BIT(5)
136#define HCR_RW_BIT BIT(31)
137
138/* System register interface to GICv3 */
139#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
140#define ICC_SGI1R S3_0_C12_C11_5
141#define ICC_SRE_EL1 S3_0_C12_C12_5
142#define ICC_SRE_EL2 S3_4_C12_C9_5
143#define ICC_SRE_EL3 S3_6_C12_C12_5
144#define ICC_CTLR_EL1 S3_0_C12_C12_4
145#define ICC_CTLR_EL3 S3_6_C12_C12_4
146#define ICC_PMR_EL1 S3_0_C4_C6_0
147#define ICC_RPR_EL1 S3_0_C12_C11_3
148#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
149#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
150#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
151#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
152#define ICC_IAR0_EL1 S3_0_C12_C8_0
153#define ICC_IAR1_EL1 S3_0_C12_C12_0
154#define ICC_EOIR0_EL1 S3_0_C12_C8_1
155#define ICC_EOIR1_EL1 S3_0_C12_C12_1
156#define ICC_SGI0R_EL1 S3_0_C12_C11_7
157
158/* register constants */
159#define ICC_SRE_ELx_SRE_BIT BIT(0)
160#define ICC_SRE_ELx_DFB_BIT BIT(1)
161#define ICC_SRE_ELx_DIB_BIT BIT(2)
162#define ICC_SRE_EL3_EN_BIT BIT(3)
163
164/* ICC SGI macros */
165#define SGIR_TGT_MASK (0xffff)
166#define SGIR_AFF1_SHIFT (16)
167#define SGIR_AFF2_SHIFT (32)
168#define SGIR_AFF3_SHIFT (48)
169#define SGIR_AFF_MASK (0xf)
170#define SGIR_INTID_SHIFT (24)
171#define SGIR_INTID_MASK (0xf)
172#define SGIR_IRM_SHIFT (40)
173#define SGIR_IRM_MASK (0x1)
174#define SGIR_IRM_TO_AFF (0)
175
176#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
177 ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
178 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
179 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
180 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
181 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
182 ((_tgt) & SGIR_TGT_MASK))
183
184/* Implementation defined register definations */
185#if defined(CONFIG_CPU_CORTEX_A72)
186
187#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
188#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT (0)
189#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT (5)
190#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT (6)
191#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT (9)
192
193#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES (2)
194#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK (0x7)
195#define CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE (1)
196#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES (1)
197#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES (2)
198#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK (0x7)
199#define CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE (1)
200
201#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0
202#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT BIT(6)
203
204#endif /* CONFIG_CPU_CORTEX_A72 */
205
206#define L1_CACHE_SHIFT (6)
207#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
208#define ARM64_CPU_INIT_SIZE L1_CACHE_BYTES
209
210#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_CPU_H_ */
Misc utilities.