Zephyr API Documentation  2.7.0-rc2
A Scalable Open Source RTOS
float_regs_riscv_gcc.h
Go to the documentation of this file.
1
6/*
7 * Copyright (c) 2019, Huang Qi <757509347@qq.com>.
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 */
11
12#ifndef _FLOAT_REGS_RISCV_GCC_H
13#define _FLOAT_REGS_RISCV_GCC_H
14
15#if !defined(__GNUC__) || !defined(CONFIG_RISCV)
16#error __FILE__ goes only with RISCV GCC
17#endif
18
19#include <toolchain.h>
20#include "float_context.h"
21
22#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
23#define RV_FPREG_WIDTH 8
24#define RV_FPREG_SAVE "fsd "
25#define RV_FPREG_LOAD "fld "
26#else
27#define RV_FPREG_WIDTH 4
28#define RV_FPREG_SAVE "fsw "
29#define RV_FPREG_LOAD "flw "
30#endif
31
49static inline void _load_all_float_registers(struct fp_register_set *regs)
50{
51 __asm__(
52 "mv t0, %0\n"
53 "mv t1, %1\n"
54 RV_FPREG_LOAD "f0, 0(t0)\n"
55 "add t0, t0, t1\n"
56 RV_FPREG_LOAD "f1, 0(t0)\n"
57 "add t0, t0, t1\n"
58 RV_FPREG_LOAD "f2, 0(t0)\n"
59 "add t0, t0, t1\n"
60 RV_FPREG_LOAD "f3, 0(t0)\n"
61 "add t0, t0, t1\n"
62 RV_FPREG_LOAD "f4, 0(t0)\n"
63 "add t0, t0, t1\n"
64 RV_FPREG_LOAD "f5, 0(t0)\n"
65 "add t0, t0, t1\n"
66 RV_FPREG_LOAD "f6, 0(t0)\n"
67 "add t0, t0, t1\n"
68 RV_FPREG_LOAD "f7, 0(t0)\n"
69 "add t0, t0, t1\n"
70 RV_FPREG_LOAD "f8, 0(t0)\n"
71 "add t0, t0, t1\n"
72 RV_FPREG_LOAD "f9, 0(t0)\n"
73 "add t0, t0, t1\n"
74 RV_FPREG_LOAD "f10, 0(t0)\n"
75 "add t0, t0, t1\n"
76 RV_FPREG_LOAD "f11, 0(t0)\n"
77 "add t0, t0, t1\n"
78 RV_FPREG_LOAD "f12, 0(t0)\n"
79 "add t0, t0, t1\n"
80 RV_FPREG_LOAD "f13, 0(t0)\n"
81 "add t0, t0, t1\n"
82 RV_FPREG_LOAD "f14, 0(t0)\n"
83 "add t0, t0, t1\n"
84 RV_FPREG_LOAD "f15, 0(t0)\n"
85 "add t0, t0, t1\n"
86 RV_FPREG_LOAD "f16, 0(t0)\n"
87 "add t0, t0, t1\n"
88 RV_FPREG_LOAD "f17, 0(t0)\n"
89 "add t0, t0, t1\n"
90 RV_FPREG_LOAD "f18, 0(t0)\n"
91 "add t0, t0, t1\n"
92 RV_FPREG_LOAD "f19, 0(t0)\n"
93 "add t0, t0, t1\n"
94 RV_FPREG_LOAD "f20, 0(t0)\n"
95 "add t0, t0, t1\n"
96 RV_FPREG_LOAD "f21, 0(t0)\n"
97 "add t0, t0, t1\n"
98 RV_FPREG_LOAD "f22, 0(t0)\n"
99 "add t0, t0, t1\n"
100 RV_FPREG_LOAD "f23, 0(t0)\n"
101 "add t0, t0, t1\n"
102 RV_FPREG_LOAD "f24, 0(t0)\n"
103 "add t0, t0, t1\n"
104 RV_FPREG_LOAD "f25, 0(t0)\n"
105 "add t0, t0, t1\n"
106 RV_FPREG_LOAD "f26, 0(t0)\n"
107 "add t0, t0, t1\n"
108 RV_FPREG_LOAD "f27, 0(t0)\n"
109 "add t0, t0, t1\n"
110 RV_FPREG_LOAD "f28, 0(t0)\n"
111 "add t0, t0, t1\n"
112 RV_FPREG_LOAD "f29, 0(t0)\n"
113 "add t0, t0, t1\n"
114 RV_FPREG_LOAD "f30, 0(t0)\n"
115 "add t0, t0, t1\n"
116 RV_FPREG_LOAD "f31, 0(t0)\n"
117 :
118 : "r"(regs), "r"(RV_FPREG_WIDTH)
119 : "t0", "t1"
120 );
121}
122
135static inline void _store_all_float_registers(struct fp_register_set *regs)
136{
137 __asm__ volatile(
138 "mv t0, %0\n\t"
139 "mv t1, %1\n\t"
140 RV_FPREG_SAVE "f0, 0(t0)\n"
141 "add t0, t0, t1\n"
142 RV_FPREG_SAVE "f1, 0(t0)\n"
143 "add t0, t0, t1\n"
144 RV_FPREG_SAVE "f2, 0(t0)\n"
145 "add t0, t0, t1\n"
146 RV_FPREG_SAVE "f3, 0(t0)\n"
147 "add t0, t0, t1\n"
148 RV_FPREG_SAVE "f4, 0(t0)\n"
149 "add t0, t0, t1\n"
150 RV_FPREG_SAVE "f5, 0(t0)\n"
151 "add t0, t0, t1\n"
152 RV_FPREG_SAVE "f6, 0(t0)\n"
153 "add t0, t0, t1\n"
154 RV_FPREG_SAVE "f7, 0(t0)\n"
155 "add t0, t0, t1\n"
156 RV_FPREG_SAVE "f8, 0(t0)\n"
157 "add t0, t0, t1\n"
158 RV_FPREG_SAVE "f9, 0(t0)\n"
159 "add t0, t0, t1\n"
160 RV_FPREG_SAVE "f10, 0(t0)\n"
161 "add t0, t0, t1\n"
162 RV_FPREG_SAVE "f11, 0(t0)\n"
163 "add t0, t0, t1\n"
164 RV_FPREG_SAVE "f12, 0(t0)\n"
165 "add t0, t0, t1\n"
166 RV_FPREG_SAVE "f13, 0(t0)\n"
167 "add t0, t0, t1\n"
168 RV_FPREG_SAVE "f14, 0(t0)\n"
169 "add t0, t0, t1\n"
170 RV_FPREG_SAVE "f15, 0(t0)\n"
171 "add t0, t0, t1\n"
172 RV_FPREG_SAVE "f16, 0(t0)\n"
173 "add t0, t0, t1\n"
174 RV_FPREG_SAVE "f17, 0(t0)\n"
175 "add t0, t0, t1\n"
176 RV_FPREG_SAVE "f18, 0(t0)\n"
177 "add t0, t0, t1\n"
178 RV_FPREG_SAVE "f19, 0(t0)\n"
179 "add t0, t0, t1\n"
180 RV_FPREG_SAVE "f20, 0(t0)\n"
181 "add t0, t0, t1\n"
182 RV_FPREG_SAVE "f21, 0(t0)\n"
183 "add t0, t0, t1\n"
184 RV_FPREG_SAVE "f22, 0(t0)\n"
185 "add t0, t0, t1\n"
186 RV_FPREG_SAVE "f23, 0(t0)\n"
187 "add t0, t0, t1\n"
188 RV_FPREG_SAVE "f24, 0(t0)\n"
189 "add t0, t0, t1\n"
190 RV_FPREG_SAVE "f25, 0(t0)\n"
191 "add t0, t0, t1\n"
192 RV_FPREG_SAVE "f26, 0(t0)\n"
193 "add t0, t0, t1\n"
194 RV_FPREG_SAVE "f27, 0(t0)\n"
195 "add t0, t0, t1\n"
196 RV_FPREG_SAVE "f28, 0(t0)\n"
197 "add t0, t0, t1\n"
198 RV_FPREG_SAVE "f29, 0(t0)\n"
199 "add t0, t0, t1\n"
200 RV_FPREG_SAVE "f30, 0(t0)\n"
201 "add t0, t0, t1\n"
202 RV_FPREG_SAVE "f31, 0(t0)\n"
203 :
204 : "r"(regs), "r"(RV_FPREG_WIDTH)
205 : "t0", "t1", "memory"
206 );
207}
208
223static inline void _load_then_store_all_float_registers(struct fp_register_set
224 *regs)
225{
226 _load_all_float_registers(regs);
227 _store_all_float_registers(regs);
228}
229#endif /* _FLOAT_REGS_ARC_GCC_H */
float_context.h
common definitions for the FPU sharing test application
RV_FPREG_SAVE
#define RV_FPREG_SAVE
Definition: float_regs_riscv_gcc.h:28
RV_FPREG_LOAD
#define RV_FPREG_LOAD
Definition: float_regs_riscv_gcc.h:29
RV_FPREG_WIDTH
#define RV_FPREG_WIDTH
Definition: float_regs_riscv_gcc.h:27
fp_register_set
Definition: float_context.h:164
toolchain.h
Macros to abstract toolchain specific capabilities.