Zephyr API Documentation
2.7.0-rc2
A Scalable Open Source RTOS
esp32_clock.h
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/*
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* Copyright (c) 2020 Mohamed ElShahawi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_
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/* System Clock Source */
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#define ESP32_CLK_SRC_XTAL 0U
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#define ESP32_CLK_SRC_PLL 1U
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#define ESP32_CLK_SRC_RTC8M 2U
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/* Supported CPU Frequencies */
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#define ESP32_CLK_CPU_26M 26U
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#define ESP32_CLK_CPU_40M 40U
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#define ESP32_CLK_CPU_80M 80U
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#define ESP32_CLK_CPU_160M 160U
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#define ESP32_CLK_CPU_240M 240U
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/* Supported XTAL Frequencies */
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#define ESP32_CLK_XTAL_40M 0U
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#define ESP32_CLK_XTAL_26M 1U
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/* Modules IDs
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* These IDs are actually offsets in CLK and RST Control registers.
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* These IDs shouldn't be changed unless there is a Hardware change
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* from Espressif.
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*
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* Basic Modules
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* Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
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*/
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#define ESP32_TIMERS_MODULE 0
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#define ESP32_SPI1_MODULE 1
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#define ESP32_UART0_MODULE 2
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#define ESP32_WDG_MODULE 3
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#define ESP32_I2S0_MODULE 4
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#define ESP32_UART1_MODULE 5
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#define ESP32_SPI2_MODULE 6
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#define ESP32_I2C_EXT0_MODULE 7
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#define ESP32_UHCI0_MODULE 8
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#define ESP32_RMT_MODULE 9
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#define ESP32_PCNT_MODULE 10
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#define ESP32_LEDC_MODULE 11
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#define ESP32_UHCI1_MODULE 12
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#define ESP32_TIMERGROUP_MODULE 13
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#define ESP32_EFUSE_MODULE 14
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#define ESP32_TIMERGROUP1_MODULE 15
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#define ESP32_SPI3_MODULE 16
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#define ESP32_PWM0_MODULE 17
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#define ESP32_I2C_EXT1_MODULE 18
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#define ESP32_CAN_MODULE 19
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#define ESP32_PWM1_MODULE 20
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#define ESP32_I2S1_MODULE 21
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#define ESP32_SPI_DMA_MODULE 22
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#define ESP32_UART2_MODULE 23
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#define ESP32_UART_MEM_MODULE 24
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#define ESP32_PWM2_MODULE 25
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#define ESP32_PWM3_MODULE 26
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/* HW Security Modules
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* Registers: DPORT_PERI_CLK_EN_REG, DPORT_PERI_RST_EN_REG
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*/
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#define ESP32_AES_MODULE 32
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#define ESP32_SHA_MODULE 33
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#define ESP32_RSA_MODULE 34
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#define ESP32_SECUREBOOT_MODULE 35
/* Secure boot reset will hold SHA & AES in reset */
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#define ESP32_DIGITAL_SIGNATURE_MODULE 36
/* Digital signature reset will hold AES & RSA in reset */
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/* WiFi/BT
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* Registers: DPORT_WIFI_CLK_EN_REG, DPORT_CORE_RST_EN_REG
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*/
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#define ESP32_SDMMC_MODULE 64
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#define ESP32_SDIO_SLAVE_MODULE 65
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#define ESP32_EMAC_MODULE 66
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#define ESP32_RNG_MODULE 67
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#define ESP32_WIFI_MODULE 68
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#define ESP32_BT_MODULE 69
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#define ESP32_WIFI_BT_COMMON_MODULE 70
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#define ESP32_BT_BASEBAND_MODULE 71
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#define ESP32_BT_LC_MODULE 72
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ */
include
dt-bindings
clock
esp32_clock.h
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