Zephyr API Documentation  2.7.0-rc2
A Scalable Open Source RTOS
esp32_clock.h
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1/*
2 * Copyright (c) 2020 Mohamed ElShahawi
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_
9
10/* System Clock Source */
11#define ESP32_CLK_SRC_XTAL 0U
12#define ESP32_CLK_SRC_PLL 1U
13#define ESP32_CLK_SRC_RTC8M 2U
14
15/* Supported CPU Frequencies */
16#define ESP32_CLK_CPU_26M 26U
17#define ESP32_CLK_CPU_40M 40U
18#define ESP32_CLK_CPU_80M 80U
19#define ESP32_CLK_CPU_160M 160U
20#define ESP32_CLK_CPU_240M 240U
21
22/* Supported XTAL Frequencies */
23#define ESP32_CLK_XTAL_40M 0U
24#define ESP32_CLK_XTAL_26M 1U
25
26/* Modules IDs
27 * These IDs are actually offsets in CLK and RST Control registers.
28 * These IDs shouldn't be changed unless there is a Hardware change
29 * from Espressif.
30 *
31 * Basic Modules
32 * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
33 */
34#define ESP32_TIMERS_MODULE 0
35#define ESP32_SPI1_MODULE 1
36#define ESP32_UART0_MODULE 2
37#define ESP32_WDG_MODULE 3
38#define ESP32_I2S0_MODULE 4
39#define ESP32_UART1_MODULE 5
40#define ESP32_SPI2_MODULE 6
41#define ESP32_I2C_EXT0_MODULE 7
42#define ESP32_UHCI0_MODULE 8
43#define ESP32_RMT_MODULE 9
44#define ESP32_PCNT_MODULE 10
45#define ESP32_LEDC_MODULE 11
46#define ESP32_UHCI1_MODULE 12
47#define ESP32_TIMERGROUP_MODULE 13
48#define ESP32_EFUSE_MODULE 14
49#define ESP32_TIMERGROUP1_MODULE 15
50#define ESP32_SPI3_MODULE 16
51#define ESP32_PWM0_MODULE 17
52#define ESP32_I2C_EXT1_MODULE 18
53#define ESP32_CAN_MODULE 19
54#define ESP32_PWM1_MODULE 20
55#define ESP32_I2S1_MODULE 21
56#define ESP32_SPI_DMA_MODULE 22
57#define ESP32_UART2_MODULE 23
58#define ESP32_UART_MEM_MODULE 24
59#define ESP32_PWM2_MODULE 25
60#define ESP32_PWM3_MODULE 26
61
62/* HW Security Modules
63 * Registers: DPORT_PERI_CLK_EN_REG, DPORT_PERI_RST_EN_REG
64 */
65#define ESP32_AES_MODULE 32
66#define ESP32_SHA_MODULE 33
67#define ESP32_RSA_MODULE 34
68#define ESP32_SECUREBOOT_MODULE 35 /* Secure boot reset will hold SHA & AES in reset */
69#define ESP32_DIGITAL_SIGNATURE_MODULE 36 /* Digital signature reset will hold AES & RSA in reset */
70
71/* WiFi/BT
72 * Registers: DPORT_WIFI_CLK_EN_REG, DPORT_CORE_RST_EN_REG
73 */
74#define ESP32_SDMMC_MODULE 64
75#define ESP32_SDIO_SLAVE_MODULE 65
76#define ESP32_EMAC_MODULE 66
77#define ESP32_RNG_MODULE 67
78#define ESP32_WIFI_MODULE 68
79#define ESP32_BT_MODULE 69
80#define ESP32_WIFI_BT_COMMON_MODULE 70
81#define ESP32_BT_BASEBAND_MODULE 71
82#define ESP32_BT_LC_MODULE 72
83
84#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ */