pcie.h

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/*
 * Copyright (c) 2019 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_
#define ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_
 
#include <stddef.h>
#include <dt-bindings/pcie/pcie.h>
#include <zephyr/types.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef uint32_t pcie_bdf_t;
 
typedef uint32_t pcie_id_t;
 
struct pcie_mbar {
        uintptr_t phys_addr;
        size_t size;
};
 
/*
 * These functions are arch-, board-, or SoC-specific.
 */
 
extern pcie_bdf_t pcie_bdf_lookup(pcie_id_t id);
 
extern uint32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg);
 
extern void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data);
 
extern bool pcie_probe(pcie_bdf_t bdf, pcie_id_t id);
 
extern bool pcie_get_mbar(pcie_bdf_t bdf,
                          unsigned int bar_index,
                          struct pcie_mbar *mbar);
 
extern bool pcie_probe_mbar(pcie_bdf_t bdf,
                            unsigned int index,
                            struct pcie_mbar *mbar);
 
extern void pcie_set_cmd(pcie_bdf_t bdf, uint32_t bits, bool on);
 
extern unsigned int pcie_alloc_irq(pcie_bdf_t bdf);
 
extern unsigned int pcie_get_irq(pcie_bdf_t bdf);
 
extern void pcie_irq_enable(pcie_bdf_t bdf, unsigned int irq);
 
extern uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id);
 
extern uint32_t pcie_get_ext_cap(pcie_bdf_t bdf, uint32_t cap_id);
 
/*
 * Configuration word 13 contains the head of the capabilities list.
 */
 
#define PCIE_CONF_CAPPTR        13U     /* capabilities pointer */
#define PCIE_CONF_CAPPTR_FIRST(w)       (((w) >> 2) & 0x3FU)
 
/*
 * The first word of every capability contains a capability identifier,
 * and a link to the next capability (or 0) in configuration space.
 */
 
#define PCIE_CONF_CAP_ID(w)             ((w) & 0xFFU)
#define PCIE_CONF_CAP_NEXT(w)           (((w) >> 10) & 0x3FU)
 
/*
 * The extended PCI Express capabilies lies at the end of the PCI configuration space
 */
 
#define PCIE_CONF_EXT_CAPPTR    64U
 
/*
 * The first word of every capability contains an extended capability identifier,
 * and a link to the next capability (or 0) in the extended configuration space.
 */
 
#define PCIE_CONF_EXT_CAP_ID(w)         ((w) & 0xFFFFU)
#define PCIE_CONF_EXT_CAP_VER(w)        (((w) >> 16) & 0xFU)
#define PCIE_CONF_EXT_CAP_NEXT(w)       (((w) >> 20) & 0xFFFU)
 
/*
 * Configuration word 0 aligns directly with pcie_id_t.
 */
 
#define PCIE_CONF_ID            0U
 
/*
 * Configuration word 1 contains command and status bits.
 */
 
#define PCIE_CONF_CMDSTAT       1U      /* command/status register */
 
#define PCIE_CONF_CMDSTAT_IO            0x00000001U  /* I/O access enable */
#define PCIE_CONF_CMDSTAT_MEM           0x00000002U  /* mem access enable */
#define PCIE_CONF_CMDSTAT_MASTER        0x00000004U  /* bus master enable */
#define PCIE_CONF_CMDSTAT_CAPS          0x00100000U  /* capabilities list */
 
/*
 * Configuration word 2 has additional function identification that
 * we only care about for debug output (PCIe shell commands).
 */
 
#define PCIE_CONF_CLASSREV      2U      /* class/revision register */
 
#define PCIE_CONF_CLASSREV_CLASS(w)     (((w) >> 24) & 0xFFU)
#define PCIE_CONF_CLASSREV_SUBCLASS(w)  (((w) >> 16) & 0xFFU)
#define PCIE_CONF_CLASSREV_PROGIF(w)    (((w) >> 8) & 0xFFU)
#define PCIE_CONF_CLASSREV_REV(w)       ((w) & 0xFFU)
 
/*
 * The only part of configuration word 3 that is of interest to us is
 * the header type, as we use it to distinguish functional endpoints
 * from bridges (which are, for our purposes, transparent).
 */
 
#define PCIE_CONF_TYPE          3U
 
#define PCIE_CONF_TYPE_BRIDGE(w)        (((w) & 0x007F0000U) != 0U)
 
/*
 * Words 4-9 are BARs are I/O or memory decoders. Memory decoders may
 * be 64-bit decoders, in which case the next configuration word holds
 * the high-order bits (and is, thus, not a BAR itself).
 */
 
#define PCIE_CONF_BAR0          4U
#define PCIE_CONF_BAR1          5U
#define PCIE_CONF_BAR2          6U
#define PCIE_CONF_BAR3          7U
#define PCIE_CONF_BAR4          8U
#define PCIE_CONF_BAR5          9U
 
#define PCIE_CONF_BAR_IO(w)             (((w) & 0x00000001U) == 0x00000001U)
#define PCIE_CONF_BAR_MEM(w)            (((w) & 0x00000001U) != 0x00000001U)
#define PCIE_CONF_BAR_64(w)             (((w) & 0x00000006U) == 0x00000004U)
#define PCIE_CONF_BAR_ADDR(w)           ((w) & ~0xfUL)
#define PCIE_CONF_BAR_FLAGS(w)          ((w) & 0xfUL)
#define PCIE_CONF_BAR_NONE              0U
 
#define PCIE_CONF_BAR_INVAL             0xFFFFFFF0U
#define PCIE_CONF_BAR_INVAL64           0xFFFFFFFFFFFFFFF0UL
 
#define PCIE_CONF_BAR_INVAL_FLAGS(w)                    \
        ((((w) & 0x00000006U) == 0x00000006U) ||        \
         (((w) & 0x00000006U) == 0x00000002U))
 
/*
 * Word 15 contains information related to interrupts.
 *
 * We're only interested in the low byte, which is [supposed to be] set by
 * the firmware to indicate which wire IRQ the device interrupt is routed to.
 */
 
#define PCIE_CONF_INTR          15U
 
#define PCIE_CONF_INTR_IRQ(w)   ((w) & 0xFFU)
#define PCIE_CONF_INTR_IRQ_NONE 0xFFU  /* no interrupt routed */
 
#define PCIE_MAX_BUS  (0xFFFFFFFF & PCIE_BDF_BUS_MASK)
#define PCIE_MAX_DEV  (0xFFFFFFFF & PCIE_BDF_DEV_MASK)
#define PCIE_MAX_FUNC (0xFFFFFFFF & PCIE_BDF_FUNC_MASK)
 
#ifdef __cplusplus
}
#endif
 
#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_ */