Zephyr API Documentation
2.7.0-rc2
A Scalable Open Source RTOS
intel_vtd.h
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/*
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* Copyright (c) 2020 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H
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#define ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H
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#ifndef _ASMLANGUAGE
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/*************\
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* Registers *
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\*************/
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#define VTD_VER_REG 0x000
/* Version */
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#define VTD_CAP_REG 0x008
/* Capability */
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#define VTD_ECAP_REG 0x010
/* Extended Capability */
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#define VTD_GCMD_REG 0x018
/* Global Command */
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#define VTD_GSTS_REG 0x01C
/* Global Status */
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#define VTD_RTADDR_REG 0x020
/* Root Table Address */
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#define VTD_CCMD_REG 0x028
/* Context Command */
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#define VTD_FSTS_REG 0x034
/* Fault Status */
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#define VTD_FECTL_REG 0x038
/* Fault Event Control Register*/
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#define VTD_FEDATA_REG 0x03C
/* Fault Event Data */
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#define VTD_FEADDR_REG 0x040
/* Fault Event Address */
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#define VTD_FEUADDR_REG 0x044
/* Fault Event Upper Address */
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#define VTD_AFLOG_REG 0x058
/* Advanced Fault Log */
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#define VTD_PMEN_REG 0x064
/* Protected Memory Enable */
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#define VTD_PLMBASE_REG 0x068
/* Protected Low Memory Base */
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#define VTD_PLMLIMIT_REG 0x06C
/* Protected Low Memory Limit */
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#define VTD_PHMBASE_REG 0x070
/* Protected High Memory Base */
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#define VTD_PHMLIMIT_REG 0x078
/* Protected High Memory Limit */
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#define VTD_IQH_REG 0x080
/* Invalidation Queue Head */
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#define VTD_IQT_REG 0x088
/* Invalidation Queue Tail */
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#define VTD_IQA_REG 0x090
/* Invalidation Queue Address */
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#define VTD_ICS_REG 0x09C
/* Invalidation Completion Status */
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#define VTD_IECTL_REG 0x0A0
/* Invalidation Completion Event Control */
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#define VTD_IEDATA_REG 0x0A4
/* Invalidation Completion Event Data */
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#define VTD_IEADDR_REG 0x0A8
/* Invalidation Completion Event Address */
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#define VTD_IEUADDR_REG 0x0AC
/* Invalidation Completion Event Upper Address */
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#define VTD_IQERCD_REG 0x0B0
/* Invalidation Queue Error Record */
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#define VTD_IRTA_REG 0x0B8
/* Interrupt Remapping Table Address */
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#define VTD_PQH_REG 0x0C0
/* Page Request Queue Head */
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#define VTD_PQT_REG 0x0C8
/* Page Request Queue Tail */
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#define VTD_PQA_REG 0x0D0
/* Page Request Queue Address */
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#define VTD_PRS_REG 0x0DC
/* Page Request Status */
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#define VTD_PECTL_REG 0x0E0
/* Page Request Event Control */
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#define VTD_PEDATA_REG 0x0E4
/* Page Request Event Data */
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#define VTD_PEADDR_REG 0x0E8
/* Page Request Event Address */
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#define VTD_PEUADDR_REG 0x0EC
/* Page Request Event Upper Address */
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#define VTD_MTRRCAP_REG 0x100
/* MTRR Capability */
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#define VTD_MTRRDEF_REG 0x108
/* MTRR Default Type */
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#define VTD_MTRR_FIX64K_00000_REG 0x120
/* Fixed-range MTRR for 64K_00000 */
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#define VTD_MTRR_FIX16K_80000_REG 0x128
/* Fixed-range MTRR for 16K_80000 */
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#define VTD_MTRR_FIX16K_A0000_REG 0x130
/* Fixed-range MTRR for 16K_A0000 */
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#define VTD_MTRR_FIX4K_C0000_REG 0x138
/* Fixed-range MTRR for 4K_C0000 */
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#define VTD_MTRR_FIX4K_C8000_REG 0x140
/* Fixed-range MTRR for 4K_C8000 */
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#define VTD_MTRR_FIX4K_D0000_REG 0x148
/* Fixed-range MTRR for 4K_D0000 */
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#define VTD_MTRR_FIX4K_D8000_REG 0x150
/* Fixed-range MTRR for 4K_D8000 */
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#define VTD_MTRR_FIX4K_E0000_REG 0x158
/* Fixed-range MTRR for 4K_E0000 */
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#define VTD_MTRR_FIX4K_E8000_REG 0x160
/* Fixed-range MTRR for 4K_E8000 */
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#define VTD_MTRR_FIX4K_F0000_REG 0x168
/* Fixed-range MTRR for 4K_F0000 */
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#define VTD_MTRR_FIX4K_F8000_REG 0x170
/* Fixed-range MTRR for 4K_F8000 */
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#define VTD_MTRR_PHYSBASE0_REG 0x180
/* Variable-range MTRR Base0 */
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#define VTD_MTRR_PHYSMASK0_REG 0x188
/* Variable-range MTRR Mask0 */
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#define VTD_MTRR_PHYSBASE1_REG 0x190
/* Variable-range MTRR Base1 */
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#define VTD_MTRR_PHYSMASK1_REG 0x198
/* Variable-range MTRR Mask1 */
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#define VTD_MTRR_PHYSBASE2_REG 0x1A0
/* Variable-range MTRR Base2 */
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#define VTD_MTRR_PHYSMASK2_REG 0x1A8
/* Variable-range MTRR Mask2 */
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#define VTD_MTRR_PHYSBASE3_REG 0x1B0
/* Variable-range MTRR Base3 */
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#define VTD_MTRR_PHYSMASK3_REG 0x1B8
/* Variable-range MTRR Mask3 */
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#define VTD_MTRR_PHYSBASE4_REG 0x1C0
/* Variable-range MTRR Base4 */
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#define VTD_MTRR_PHYSMASK4_REG 0x1C8
/* Variable-range MTRR Mask4 */
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#define VTD_MTRR_PHYSBASE5_REG 0x1D0
/* Variable-range MTRR Base5 */
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#define VTD_MTRR_PHYSMASK5_REG 0x1D8
/* Variable-range MTRR Mask5 */
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#define VTD_MTRR_PHYSBASE6_REG 0x1E0
/* Variable-range MTRR Base6 */
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#define VTD_MTRR_PHYSMASK6_REG 0x1E8
/* Variable-range MTRR Mask6 */
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#define VTD_MTRR_PHYSBASE7_REG 0x1F0
/* Variable-range MTRR Base7 */
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#define VTD_MTRR_PHYSMASK7_REG 0x1F8
/* Variable-range MTRR Mask7 */
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#define VTD_MTRR_PHYSBASE8_REG 0x200
/* Variable-range MTRR Base8 */
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#define VTD_MTRR_PHYSMASK8_REG 0x208
/* Variable-range MTRR Mask8 */
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#define VTD_MTRR_PHYSBASE9_REG 0x210
/* Variable-range MTRR Base9 */
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#define VTD_MTRR_PHYSMASK9_REG 0x218
/* Variable-range MTRR Mask9 */
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#define VTD_VCCAP_REG 0xE00
/* Virtual Command Capability */
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#define VTD_VCMD 0xE10
/* Virtual Command */
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#define VTD_VCRSP 0xE20
/* Virtual Command Response */
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/* Global Command Register details */
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#define VTD_GCMD_CFI 23
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#define VTD_GCMD_SIRTP 24
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#define VTD_GCMD_IRE 25
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#define VTD_GCMD_QIE 26
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#define VTD_GCMD_WBF 27
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#define VTD_GCMD_EAFL 28
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#define VTD_GCMD_SFL 29
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#define VTD_GCMD_SRTP 30
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#define VTD_GCMD_TE 31
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/* Global Status Register details */
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#define VTD_GSTS_CFIS 23
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#define VTD_GSTS_SIRTPS 24
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#define VTD_GSTS_IRES 25
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#define VTD_GSTS_QIES 26
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#define VTD_GSTS_WBFS 27
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#define VTD_GSTS_EAFLS 28
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#define VTD_GSTS_SFLS 29
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#define VTD_GSTS_SRTPS 30
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#define VTD_GSTS_TES 31
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/* Interrupt Remapping Table Address Register details */
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#define VTD_IRTA_SIZE_MASK 0x00000000000000FF
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#define VTD_IRTA_EIME 11
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#define VTD_IRTA_ADDR_SHIFT 12
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#define VTD_IRTA_REG_GEN_CONTENT(addr, size, mode) \
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(0 | \
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(addr << VTD_IRTA_ADDR_SHIFT) | \
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(mode) | (size & VTD_IRTA_SIZE_MASK))
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#endif
/* _ASMLANGUAGE */
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#endif
/* ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H */
include
arch
x86
intel_vtd.h
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