16#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_SYSCALL_H_
17#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_SYSCALL_H_
19#define _SVC_CALL_CONTEXT_SWITCH 0
20#define _SVC_CALL_IRQ_OFFLOAD 1
21#define _SVC_CALL_RUNTIME_EXCEPT 2
22#define _SVC_CALL_SYSTEM_CALL 3
24#ifdef CONFIG_USERSPACE
45 register uint32_t r1 __asm__(
"r1") = arg2;
46 register uint32_t r2 __asm__(
"r2") = arg3;
47 register uint32_t r3 __asm__(
"r3") = arg4;
48 register uint32_t r4 __asm__(
"r4") = arg5;
49 register uint32_t r5 __asm__(
"r5") = arg6;
50 register uint32_t r6 __asm__(
"r6") = call_id;
52 __asm__
volatile(
"svc %[svid]\n"
53 :
"=r"(
ret),
"=r"(r1),
"=r"(r2),
"=r"(r3)
54 : [svid]
"i" (_SVC_CALL_SYSTEM_CALL),
55 "r" (
ret),
"r" (r1),
"r" (r2),
"r" (r3),
56 "r" (r4),
"r" (r5),
"r" (r6)
57 :
"r8",
"memory",
"ip");
68 register uint32_t r1 __asm__(
"r1") = arg2;
69 register uint32_t r2 __asm__(
"r2") = arg3;
70 register uint32_t r3 __asm__(
"r3") = arg4;
71 register uint32_t r4 __asm__(
"r4") = arg5;
72 register uint32_t r6 __asm__(
"r6") = call_id;
74 __asm__
volatile(
"svc %[svid]\n"
75 :
"=r"(
ret),
"=r"(r1),
"=r"(r2),
"=r"(r3)
76 : [svid]
"i" (_SVC_CALL_SYSTEM_CALL),
77 "r" (
ret),
"r" (r1),
"r" (r2),
"r" (r3),
79 :
"r8",
"memory",
"ip");
89 register uint32_t r1 __asm__(
"r1") = arg2;
90 register uint32_t r2 __asm__(
"r2") = arg3;
91 register uint32_t r3 __asm__(
"r3") = arg4;
92 register uint32_t r6 __asm__(
"r6") = call_id;
94 __asm__
volatile(
"svc %[svid]\n"
95 :
"=r"(
ret),
"=r"(r1),
"=r"(r2),
"=r"(r3)
96 : [svid]
"i" (_SVC_CALL_SYSTEM_CALL),
97 "r" (
ret),
"r" (r1),
"r" (r2),
"r" (r3),
99 :
"r8",
"memory",
"ip");
109 register uint32_t r1 __asm__(
"r1") = arg2;
110 register uint32_t r2 __asm__(
"r2") = arg3;
111 register uint32_t r6 __asm__(
"r6") = call_id;
113 __asm__
volatile(
"svc %[svid]\n"
114 :
"=r"(
ret),
"=r"(r1),
"=r"(r2)
115 : [svid]
"i" (_SVC_CALL_SYSTEM_CALL),
116 "r" (
ret),
"r" (r1),
"r" (r2),
"r" (r6)
117 :
"r8",
"memory",
"r3",
"ip");
126 register uint32_t r1 __asm__(
"r1") = arg2;
127 register uint32_t r6 __asm__(
"r6") = call_id;
129 __asm__
volatile(
"svc %[svid]\n"
130 :
"=r"(
ret),
"=r"(r1)
131 : [svid]
"i" (_SVC_CALL_SYSTEM_CALL),
132 "r" (
ret),
"r" (r1),
"r" (r6)
133 :
"r8",
"memory",
"r2",
"r3",
"ip");
142 register uint32_t r6 __asm__(
"r6") = call_id;
144 __asm__
volatile(
"svc %[svid]\n"
146 : [svid]
"i" (_SVC_CALL_SYSTEM_CALL),
148 :
"r8",
"memory",
"r1",
"r2",
"r3",
"ip");
155 register uint32_t r6 __asm__(
"r6") = call_id;
157 __asm__
volatile(
"svc %[svid]\n"
159 : [svid]
"i" (_SVC_CALL_SYSTEM_CALL),
161 :
"r8",
"memory",
"r1",
"r2",
"r3",
"ip");
168#if defined(CONFIG_CPU_CORTEX_M)
172 __asm__
volatile(
"mrs %0, IPSR\n\t" :
"=r"(value));
178 return z_arm_thread_is_in_user_mode();
static uintptr_t arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, uintptr_t call_id)
Definition: syscall.h:84
static uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2, uintptr_t call_id)
Definition: syscall.h:122
static uintptr_t arch_syscall_invoke1(uintptr_t arg1, uintptr_t call_id)
Definition: syscall.h:138
static uintptr_t arch_syscall_invoke0(uintptr_t call_id)
Definition: syscall.h:152
static bool arch_is_user_context(void)
Definition: syscall.h:166
static uintptr_t arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, uintptr_t arg5, uintptr_t call_id)
Definition: syscall.h:62
static uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t call_id)
Definition: syscall.h:104
static uintptr_t arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, uintptr_t arg5, uintptr_t arg6, uintptr_t call_id)
Definition: syscall.h:39
ARM AArch32 public kernel miscellaneous.
static ZTEST_BMEM volatile int ret
Definition: k_float_disable.c:28
__UINT32_TYPE__ uint32_t
Definition: stdint.h:60
__UINTPTR_TYPE__ uintptr_t
Definition: stdint.h:75