16#ifndef ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_
17#define ZEPHYR_INCLUDE_ARCH_ARC_ARCH_H_
35#ifdef CONFIG_ARC_CONNECT
39#ifdef CONFIG_ISA_ARCV2
41#ifdef CONFIG_ARC_HAS_SECURE
53#define ARCH_STACK_PTR_ALIGN 8
55#define ARCH_STACK_PTR_ALIGN 4
66#ifdef CONFIG_ARC_CORE_MPU
67#if CONFIG_ARC_MPU_VER == 2
68#define Z_ARC_MPU_ALIGN 2048
69#elif (CONFIG_ARC_MPU_VER == 3) || (CONFIG_ARC_MPU_VER == 4) || (CONFIG_ARC_MPU_VER == 6)
70#define Z_ARC_MPU_ALIGN 32
72#error "Unsupported MPU version"
76#ifdef CONFIG_MPU_STACK_GUARD
77#define Z_ARC_STACK_GUARD_SIZE Z_ARC_MPU_ALIGN
79#define Z_ARC_STACK_GUARD_SIZE 0
94#ifdef CONFIG_MPU_STACK_GUARD
95#define ARCH_KERNEL_STACK_RESERVED Z_ARC_STACK_GUARD_SIZE
96#define ARCH_KERNEL_STACK_OBJ_ALIGN Z_ARC_MPU_ALIGN
99#ifdef CONFIG_USERSPACE
107#ifdef CONFIG_MPU_STACK_GUARD
124#define ARCH_THREAD_STACK_RESERVED (Z_ARC_STACK_GUARD_SIZE + \
125 CONFIG_PRIVILEGED_STACK_SIZE)
126#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
130#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
131 (ROUND_UP((size), Z_ARC_MPU_ALIGN))
132BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
133 "improper privilege stack size");
136#ifdef CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
152#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
153 Z_POW2_CEIL(ROUND_UP((size), Z_ARC_MPU_ALIGN))
154#define ARCH_THREAD_STACK_OBJ_ALIGN(size) \
155 ARCH_THREAD_STACK_SIZE_ADJUST(size)
156#define ARCH_THREAD_STACK_RESERVED 0
170#define ARCH_THREAD_STACK_RESERVED CONFIG_PRIVILEGED_STACK_SIZE
171#define ARCH_THREAD_STACK_SIZE_ADJUST(size) \
172 (ROUND_UP((size), Z_ARC_MPU_ALIGN))
173#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
175BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
176 "improper privilege stack size");
182#ifdef CONFIG_MPU_STACK_GUARD
197#define ARCH_THREAD_STACK_RESERVED Z_ARC_STACK_GUARD_SIZE
198#define ARCH_THREAD_STACK_OBJ_ALIGN(size) Z_ARC_MPU_ALIGN
210#define K_MEM_PARTITION_P_NA_U_NA AUX_MPU_ATTR_N
211#define K_MEM_PARTITION_P_RW_U_RW (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \
212 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
213#define K_MEM_PARTITION_P_RW_U_RO (AUX_MPU_ATTR_UR | \
214 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
215#define K_MEM_PARTITION_P_RW_U_NA (AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR)
216#define K_MEM_PARTITION_P_RO_U_RO (AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR)
217#define K_MEM_PARTITION_P_RO_U_NA (AUX_MPU_ATTR_KR)
220#define K_MEM_PARTITION_P_RWX_U_RWX (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_UR | \
221 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | \
222 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
223#define K_MEM_PARTITION_P_RWX_U_RX (AUX_MPU_ATTR_UR | \
224 AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | \
225 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
226#define K_MEM_PARTITION_P_RX_U_RX (AUX_MPU_ATTR_UR | \
228 AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE)
230#define K_MEM_PARTITION_IS_WRITABLE(attr) \
232 int __is_writable__; \
233 switch (attr & (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW)) { \
234 case (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW): \
235 case AUX_MPU_ATTR_UW: \
236 case AUX_MPU_ATTR_KW: \
237 __is_writable__ = 1; \
240 __is_writable__ = 0; \
245#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \
246 ((attr) & (AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE))
248#if CONFIG_ARC_MPU_VER == 2
249#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
250 BUILD_ASSERT(!(((size) & ((size) - 1))) && (size) >= Z_ARC_MPU_ALIGN \
251 && !((uint32_t)(start) & ((size) - 1)), \
252 "the size of the partition must be power of 2" \
253 " and greater than or equal to the mpu adddress alignment." \
254 "start address of the partition must align with size.")
255#elif CONFIG_ARC_MPU_VER == 4
256#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
257 BUILD_ASSERT((size) % Z_ARC_MPU_ALIGN == 0 && \
258 (size) >= Z_ARC_MPU_ALIGN && \
259 (uint32_t)(start) % Z_ARC_MPU_ALIGN == 0, \
260 "the size of the partition must align with 32" \
261 " and greater than or equal to 32." \
262 "start address of the partition must align with 32.")
static ALWAYS_INLINE void arch_nop(void)
Definition: arch.h:269
uint32_t k_mem_partition_attr_t
Definition: arch.h:267
ARCv2 public error handling.
ARCv2 public exception handling.
ARCv2 public kernel miscellaneous.
ARCv2 ARC Connect driver.
Per-arch thread definition.
ARCv2 public interrupt handling.
ARCv2 auxiliary registers definitions.
#define ALWAYS_INLINE
Definition: common.h:116
__UINT32_TYPE__ uint32_t
Definition: stdint.h:60
Software-managed ISR table.